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authorSubrata Banik <subrata.banik@intel.com>2021-10-25 11:23:54 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-10-25 17:14:35 +0000
commitac1bba8e34ea7b2c9112b19c4d7e63e74949a899 (patch)
treed4e1dfef6e305930f6ff2dc9a79b027207e0fd5f /src/cpu/intel/car
parent66b2f2015688033a0d46d8fcc5d3f08aea1fb8b2 (diff)
soc/intel/common: Skip CSE post hook when CSE is disabled
This patch fixes regression introduced by commit bee4bb5f0 (soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM) FAFT test case fail when doing `firmware_DevMode` test. If CSE is already hidden then accessing CSE registers would be wrong and will receive junk, hence, return as CSE is already disabled. BUG=b:203061531 TEST=Brya system can boot to OS with recovery mode. Change-Id: I2046eb19716c397a066c2c41e1b027a256bd6cf9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/cpu/intel/car')
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