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authorNico Huber <nico.h@gmx.de>2018-05-27 13:52:28 +0200
committerNico Huber <nico.h@gmx.de>2018-05-31 15:10:21 +0000
commit654cc2fe109ea1be4d22447b3d0e6eb22a75b550 (patch)
treedf38c7f7fae159a0549c31acd39b4dd8648fc538 /src/cpu/intel/car
parent6197b7698875271a2b72e730040ec7e9260a454c (diff)
{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate
Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/cpu/intel/car')
-rw-r--r--src/cpu/intel/car/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 555c3846b4..03a94eebd1 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -74,7 +74,7 @@ void *setup_stack_and_mtrrs(void)
postcar_frame_init_lowmem(&pcf);
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */