diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-08 00:08:55 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-06-13 12:26:34 +0000 |
| commit | dc6bb6cb82110a903ff56d7e816d575e8d2242e2 (patch) | |
| tree | 8329fd7c070bc669c84064a0103210a8581ee415 /src/cpu/intel/car/p4-netburst | |
| parent | ed318f2001c0616651f5fff4be5dbe10f4d66702 (diff) | |
cpu/intel/car: Use symbols for CAR MTRR setup
Change-Id: I32d7337ccf8005c7fb65d2efea40c122093d4dd9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/intel/car/p4-netburst')
| -rw-r--r-- | src/cpu/intel/car/p4-netburst/cache_as_ram.S | 32 |
1 files changed, 14 insertions, 18 deletions
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 1277ef4d55..806102f0b0 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -8,14 +8,6 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - -#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) -#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" -#endif -#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE - .global bootblock_pre_c_entry .code32 @@ -219,14 +211,16 @@ sipi_complete: /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + movl $_car_mtrr_start, %eax + orl $MTRR_TYPE_WRBACK, %eax xorl %edx, %edx wrmsr /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $_car_mtrr_mask, %eax + orl $MTRR_PHYS_MASK_VALID, %eax wrmsr post_code(0x2b) @@ -277,12 +271,13 @@ no_msr_11e: /* Cache the whole rom to fetch microcode updates */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax + movl $_rom_mtrr_base, %eax + orl $MTRR_TYPE_WRPROT, %eax wrmsr - movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $_rom_mtrr_mask, %eax + orl $MTRR_PHYS_MASK_VALID, %eax wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ @@ -332,13 +327,13 @@ cache_rom: * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html */ movl $_program, %eax - andl $(~(XIP_ROM_SIZE - 1)), %eax + andl $_xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr - movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $_xip_mtrr_mask, %eax + orl $MTRR_PHYS_MASK_VALID, %eax wrmsr fill_cache: @@ -352,8 +347,9 @@ fill_cache: /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax - movl $CACHE_AS_RAM_BASE, %edi - movl $(CACHE_AS_RAM_SIZE >> 2), %ecx + movl $_car_mtrr_start, %edi + movl $_car_mtrr_size, %ecx + shr $2, %ecx rep stosl /* Setup the stack. */ |