- Initial checkin of the freebios2 tree

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 248 insertions, 0 deletions

diff --git a/src/cpu/i386/entry16.inc b/src/cpu/i386/entry16.inc
new file mode 100644
index 0000000000..c357504735
--- /dev/null
+++ b/src/cpu/i386/entry16.inc
@@ -0,0 +1,112 @@
+/*
+This software and ancillary information (herein called SOFTWARE )
+called LinuxBIOS          is made available under the terms described
+here.  The SOFTWARE has been approved for release with associated
+LA-CC Number 00-34   .  Unless otherwise indicated, this SOFTWARE has
+been authored by an employee or employees of the University of
+California, operator of the Los Alamos National Laboratory under
+Contract No. W-7405-ENG-36 with the U.S. Department of Energy.  The
+U.S. Government has rights to use, reproduce, and distribute this
+SOFTWARE.  The public may copy, distribute, prepare derivative works
+and publicly display this SOFTWARE without charge, provided that this
+Notice and any statement of authorship are reproduced on all copies.
+Neither the Government nor the University makes any warranty, express
+or implied, or assumes any liability or responsibility for the use of
+this SOFTWARE.  If SOFTWARE is modified to produce derivative works,
+such modified SOFTWARE should be clearly marked, so as not to confuse
+it with the version available from LANL.
+ */
+/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
+ * rminnich@lanl.gov
+ */
+
+
+/** Start code to put an i386 or later processor into 32-bit 
+ * protected mode. 
+ */
+
+/* .section ".rom.text" */
+#include <arch/rom_segs.h>
+.code16
+.globl	EXT(_start)
+.type EXT(_start), @function
+
+EXT(_start): 
+	cli
+
+/* thanks to kmliu@sis.tw.com for this TBL fix ... */
+/**/
+/* IMMEDIATELY invalidate the translation lookaside buffer before executing*/
+/* any further code.  Even though paging is disabled we could still get*/
+/*false address translations due to the TLB if we didn't invalidate it.*/
+/**/
+	xorl	%eax, %eax
+	movl	%eax, %cr3    /* Invalidate TLB*/
+
+	/* invalidate the cache */
+	invd 
+
+	/* Note: gas handles memory addresses in 16 bit code very poorly.
+	 * In particular it doesn't appear to have a directive allowing you
+	 * associate a section or even an absolute offset with a segment register.
+	 *
+	 * This means that anything except cs:ip relative offsets are
+	 * a real pain in 16 bit mode.  And explains why it is almost
+	 * imposible to get gas to do lgdt correctly.
+	 *
+	 * One way to work around this is to have the linker do the
+	 * math instead of the assembler.  This solves the very
+	 * pratical problem of being able to write code that can
+	 * be relocated.
+	 *
+	 * An lgdt call before we have memory enabled cannot be 
+	 * position independent, as we cannot execute a call
+	 * instruction to get our current instruction pointer.
+	 * So while this code is relocateable it isn't arbitrarily
+	 * relocatable.
+	 *
+	 * The criteria for relocation have been relaxed to their 
+	 * utmost, so that we can use the same code for both
+	 * our initial entry point and startup of the second cpu.
+	 * The code assumes when executing at _start that:
+	 * (((cs & 0xfff) == 0) and (ip == _start & 0xffff))
+	 * or
+	 * ((cs == anything) and (ip == 0)).
+	 *
+	 * The restrictions in reset16.inc mean that _start initially
+	 * must be loaded at or above 0xffff0000 or below 0x100000.
+	 *
+	 * The linker scripts computs gdtptr16_offset by simply returning
+	 * the low 16 bits.  This means that the intial segment used
+	 * when start is called must be 64K aligned.  This should not
+	 * restrict the address as the ip address can be anything.
+	 */
+
+	movw	%cs, %ax
+	shlw	$4, %ax
+	movw	$EXT(gdtptr16_offset), %bx
+	subw	%ax, %bx
+	data32  lgdt %cs:(%bx)
+
+	movl	%cr0, %eax
+	andl	$0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
+	orl	$0x60000001, %eax /* CD, NW, PE = 1 */
+	movl	%eax, %cr0
+
+	/* Now that we are in protected mode jump to a 32 bit code segment. */
+	data32	ljmp	$ROM_CODE_SEG, $__protected_start
+
+/** The gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
+ * at 0x18; these are Linux-compatible. 
+ */
+
+.align	4
+.globl EXT(gdtptr16)
+EXT(gdtptr16):
+	.word	gdt_end - gdt -1 /* compute the table limit */
+	.long	gdt		 /* we know the offset */
+
+.globl EXT(_estart)
+EXT(_estart):
+	.code32
+
diff --git a/src/cpu/i386/entry16.lds b/src/cpu/i386/entry16.lds
new file mode 100644
index 0000000000..db37e66302
--- /dev/null
+++ b/src/cpu/i386/entry16.lds
@@ -0,0 +1,2 @@
+	gdtptr16_offset = gdtptr16 & 0xffff;
+	_start_offset = _start & 0xffff;
diff --git a/src/cpu/i386/entry32.inc b/src/cpu/i386/entry32.inc
new file mode 100644
index 0000000000..8ccd638e95
--- /dev/null
+++ b/src/cpu/i386/entry32.inc
@@ -0,0 +1,55 @@
+/* For starting linuxBIOS in protected mode */
+
+#include <arch/rom_segs.h>
+
+/* 	.section ".rom.text" */
+	.code32
+
+	.align	4
+.globl EXT(gdtptr)
+
+gdt:
+EXT(gdtptr):
+	.word	gdt_end - gdt -1 /* compute the table limit */
+	.long	gdt		 /* we know the offset */
+	.word	0
+
+/* flat code segment */
+	.word	0xffff, 0x0000		
+	.byte	0x00, 0x9b, 0xcf, 0x00	
+	
+/* flat data segment */
+	.word	0xffff, 0x0000		
+	.byte	0x00, 0x93, 0xcf, 0x00	
+
+gdt_end:
+	
+
+/*
+ *	When we come here we are in protected mode. We expand 
+ *	the stack and copies the data segment from ROM to the
+ *	memory.
+ *
+ *	After that, we call the chipset bootstrap routine that
+ *	does what is left of the chipset initialization. 
+ *
+ *	NOTE aligned to 4 so that we are sure that the prefetch
+ *	cache will be reloaded.
+ */
+	.align	4
+.globl EXT(protected_start)
+EXT(protected_start):
+
+	lgdt	%cs:gdtptr
+	ljmp	$ROM_CODE_SEG, $__protected_start
+	
+__protected_start:
+	intel_chip_post_macro(0x10)	/* post 10 */
+
+	movw	$ROM_DATA_SEG, %ax
+	movw	%ax, %ds
+	movw	%ax, %es
+	movw	%ax, %ss
+	movw	%ax, %fs
+	movw	%ax, %gs
+
diff --git a/src/cpu/i386/entry32.lds b/src/cpu/i386/entry32.lds
new file mode 100644
index 0000000000..37a75ba6ae
--- /dev/null
+++ b/src/cpu/i386/entry32.lds
@@ -0,0 +1,14 @@
+/*
+	_cache_ram_seg_base = DEFINED(CACHE_RAM_BASE)? CACHE_RAM_BASE - _rodata : 0;
+	_cache_ram_seg_base_low    = (_cache_ram_seg_base) & 0xffff;
+	_cache_ram_seg_base_middle = (_cache_ram_seg_base >> 16) & 0xff;
+	_cache_ram_seg_base_high   = (_cache_ram_seg_base >> 24) & 0xff;
+
+	_rom_code_seg_base =  _ltext - _text;
+	_rom_code_seg_base_low    = (_rom_code_seg_base) & 0xffff;
+	_rom_code_seg_base_middle = (_rom_code_seg_base >> 16) & 0xff;
+	_rom_code_seg_base_high   = (_rom_code_seg_base >> 24) & 0xff;
+*/
+
+
+
diff --git a/src/cpu/i386/reset16.inc b/src/cpu/i386/reset16.inc
new file mode 100644
index 0000000000..7c911d9ff2
--- /dev/null
+++ b/src/cpu/i386/reset16.inc
@@ -0,0 +1,27 @@
+	.section ".reset"
+	.code16
+.globl	EXT(reset_vector)
+EXT(reset_vector):
+#if _ROMBASE >= 0xffff0000
+	/* Hmm.
+	 * _start_offset is the low 16 bits of _start.
+	 * Theoretically we should have problems but it compiles
+	 * and links properly with binutils 2.9.5 & 2.10.90
+	 * This is probably a case that needs fixing in binutils.
+	 * And then we can just use _start.
+	 * We also need something like the assume directive in
+	 * other assemblers to tell it where the segment registers
+	 * are pointing in memory right now.
+	 */
+	jmp	EXT(_start_offset)
+#elif (_ROMBASE < 0x100000)
+	ljmp	$((_ROMBASE & 0xf0000)>>4),$EXT(_start_offset);
+#else
+#error	_ROMBASE is an unsupported value
+#endif
+
+	. = 0x8;
+	.code32
+	jmp	EXT(protected_start)
+
+	.previous
diff --git a/src/cpu/i386/reset16.lds b/src/cpu/i386/reset16.lds
new file mode 100644
index 0000000000..80f2fc0c6f
--- /dev/null
+++ b/src/cpu/i386/reset16.lds
@@ -0,0 +1,14 @@
+/*
+ *      _ROMTOP                 : The top of the rom used where we
+ *				  need to put the reset vector.
+ */
+
+SECTIONS {
+	_ROMTOP = (_ROMBASE >= 0xffff0000)? 0xfffffff0 : 0xffff0;
+	. = _ROMTOP;
+	.reset . : {
+		*(.reset)
+		. = 15 ;
+		BYTE(0x00);
+	} 
+}
diff --git a/src/cpu/i386/reset32.inc b/src/cpu/i386/reset32.inc
new file mode 100644
index 0000000000..ec743b70cc
--- /dev/null
+++ b/src/cpu/i386/reset32.inc
@@ -0,0 +1,10 @@
+	.section ".reset"
+	.code16
+.globl	EXT(reset_vector)
+EXT(reset_vector):
+
+	. = 0x8;
+	.code32
+	jmp	EXT(protected_start)
+
+	.previous
diff --git a/src/cpu/i386/reset32.lds b/src/cpu/i386/reset32.lds
new file mode 100644
index 0000000000..fa6db86b1a
--- /dev/null
+++ b/src/cpu/i386/reset32.lds
@@ -0,0 +1,14 @@
+/*
+ *      _ROMTOP                 : The top of the rom used where we
+ *				  need to put the reset vector.
+ */
+
+SECTIONS {
+	_ROMTOP = _ROMBASE + ROM_IMAGE_SIZE - 0x10;
+	. = _ROMTOP;
+	.reset (.): {
+		*(.reset)
+		. = 15 ;
+		BYTE(0x00);
+	} 
+}