- remove deprecated directories

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

10 files changed, 0 insertions, 301 deletions

diff --git a/src/cpu/i386/bist32.inc b/src/cpu/i386/bist32.inc
deleted file mode 100644
index d2fb98cdc3..0000000000
--- a/src/cpu/i386/bist32.inc
+++ /dev/null
@@ -1,4 +0,0 @@
-
-	/* Carefully print the failure if the built in self test did not pass */
-	testl	%eax, %eax
-	jnz	bist32_fail
diff --git a/src/cpu/i386/bist32_fail.inc b/src/cpu/i386/bist32_fail.inc
deleted file mode 100644
index f467b065bc..0000000000
--- a/src/cpu/i386/bist32_fail.inc
+++ /dev/null
@@ -1,44 +0,0 @@
-
-
-	jmp bist32_fail_0
-bist32_fail:
-	movl	%eax, %ebp
-
-#if 1
-#define SIO_BASE  0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA  SIO_BASE+1
-#define SIO_WRITE_CONFIG(value, reg) \
-	movb	reg, %al		; \
-	outb	%al, $(SIO_INDEX)	; \
-	movb	value, %al		; \
-	outb	%al, $(SIO_DATA)
-
-#define SIO_READ_CONFIG(reg) \
-	movb	reg, %al		; \
-	outb	%al, $(SIO_INDEX)	; \
-	inb	$(SIO_DATA), %al
-
-#define SIO_SET_LOGICAL_DEVICE(device) \
-	SIO_WRITE_CONFIG(device, $0x07)
-
-	/* Enable serial 1 */
-	SIO_SET_LOGICAL_DEVICE($3)
-	SIO_WRITE_CONFIG($1, $0x30)
-	SIO_WRITE_CONFIG($0x3, $0x60)
-	SIO_WRITE_CONFIG($0xf8, $0x61)
-
-#endif	
-	CALLSP(serial_init)
-	CONSOLE_DEBUG_TX_STRING($str_bist_failed)
-	CONSOLE_DEBUG_TX_HEX32(%ebp)
-	CONSOLE_DEBUG_TX_STRING($str_bist_newline)
-	jmp .Lhlt
-
-bist32_fail_0:
-
-.section ".rom.data"
-str_bist_failed:	.string "BIST failed: "
-str_bist_newline:	.string "\r\n"
-.previous
-
diff --git a/src/cpu/i386/entry16.inc b/src/cpu/i386/entry16.inc
deleted file mode 100644
index f9e921f291..0000000000
--- a/src/cpu/i386/entry16.inc
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
-This software and ancillary information (herein called SOFTWARE )
-called LinuxBIOS          is made available under the terms described
-here.  The SOFTWARE has been approved for release with associated
-LA-CC Number 00-34   .  Unless otherwise indicated, this SOFTWARE has
-been authored by an employee or employees of the University of
-California, operator of the Los Alamos National Laboratory under
-Contract No. W-7405-ENG-36 with the U.S. Department of Energy.  The
-U.S. Government has rights to use, reproduce, and distribute this
-SOFTWARE.  The public may copy, distribute, prepare derivative works
-and publicly display this SOFTWARE without charge, provided that this
-Notice and any statement of authorship are reproduced on all copies.
-Neither the Government nor the University makes any warranty, express
-or implied, or assumes any liability or responsibility for the use of
-this SOFTWARE.  If SOFTWARE is modified to produce derivative works,
-such modified SOFTWARE should be clearly marked, so as not to confuse
-it with the version available from LANL.
- */
-/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
- * rminnich@lanl.gov
- */
-
-
-/** Start code to put an i386 or later processor into 32-bit 
- * protected mode. 
- */
-
-/* .section ".rom.text" */
-#include <arch/rom_segs.h>
-.code16
-.globl _start
-.type _start, @function
-
-_start: 
-	cli
-	/* Save the BIST result */
-	movl	%eax, %ebp
-
-/* thanks to kmliu@sis.tw.com for this TBL fix ... */
-/**/
-/* IMMEDIATELY invalidate the translation lookaside buffer before executing*/
-/* any further code.  Even though paging is disabled we could still get*/
-/*false address translations due to the TLB if we didn't invalidate it.*/
-/**/
-	xorl	%eax, %eax
-	movl	%eax, %cr3    /* Invalidate TLB*/
-
-	/* invalidate the cache */
-	invd 
-
-	/* Note: gas handles memory addresses in 16 bit code very poorly.
-	 * In particular it doesn't appear to have a directive allowing you
-	 * associate a section or even an absolute offset with a segment register.
-	 *
-	 * This means that anything except cs:ip relative offsets are
-	 * a real pain in 16 bit mode.  And explains why it is almost
-	 * imposible to get gas to do lgdt correctly.
-	 *
-	 * One way to work around this is to have the linker do the
-	 * math instead of the assembler.  This solves the very
-	 * pratical problem of being able to write code that can
-	 * be relocated.
-	 *
-	 * An lgdt call before we have memory enabled cannot be 
-	 * position independent, as we cannot execute a call
-	 * instruction to get our current instruction pointer.
-	 * So while this code is relocateable it isn't arbitrarily
-	 * relocatable.
-	 *
-	 * The criteria for relocation have been relaxed to their 
-	 * utmost, so that we can use the same code for both
-	 * our initial entry point and startup of the second cpu.
-	 * The code assumes when executing at _start that:
-	 * (((cs & 0xfff) == 0) and (ip == _start & 0xffff))
-	 * or
-	 * ((cs == anything) and (ip == 0)).
-	 *
-	 * The restrictions in reset16.inc mean that _start initially
-	 * must be loaded at or above 0xffff0000 or below 0x100000.
-	 *
-	 * The linker scripts computs gdtptr16_offset by simply returning
-	 * the low 16 bits.  This means that the intial segment used
-	 * when start is called must be 64K aligned.  This should not
-	 * restrict the address as the ip address can be anything.
-	 */
-
-	movw	%cs, %ax
-	shlw	$4, %ax
-	movw	$gdtptr16_offset, %bx
-	subw	%ax, %bx
-	data32  lgdt %cs:(%bx)
-
-	movl	%cr0, %eax
-	andl	$0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
-	orl	$0x60000001, %eax /* CD, NW, PE = 1 */
-	movl	%eax, %cr0
-
-	/* Restore BIST to %eax */
-	movl	%ebp, %eax
-
-	/* Now that we are in protected mode jump to a 32 bit code segment. */
-	data32	ljmp	$ROM_CODE_SEG, $__protected_start
-
-/** The gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
- * at 0x18; these are Linux-compatible. 
- */
-
-.align	4
-.globl gdtptr16
-gdtptr16:
-	.word	gdt_end - gdt -1 /* compute the table limit */
-	.long	gdt		 /* we know the offset */
-
-.globl _estart
-_estart:
-	.code32
-
diff --git a/src/cpu/i386/entry16.lds b/src/cpu/i386/entry16.lds
deleted file mode 100644
index db37e66302..0000000000
--- a/src/cpu/i386/entry16.lds
+++ /dev/null
@@ -1,2 +0,0 @@
-	gdtptr16_offset = gdtptr16 & 0xffff;
-	_start_offset = _start & 0xffff;
diff --git a/src/cpu/i386/entry32.inc b/src/cpu/i386/entry32.inc
deleted file mode 100644
index 3d30a3f85f..0000000000
--- a/src/cpu/i386/entry32.inc
+++ /dev/null
@@ -1,61 +0,0 @@
-/* For starting linuxBIOS in protected mode */
-
-#include <arch/rom_segs.h>
-
-/* 	.section ".rom.text" */
-	.code32
-
-	.align	4
-.globl gdtptr
-
-gdt:
-gdtptr:
-	.word	gdt_end - gdt -1 /* compute the table limit */
-	.long	gdt		 /* we know the offset */
-	.word	0
-
-/* flat code segment */
-	.word	0xffff, 0x0000		
-	.byte	0x00, 0x9b, 0xcf, 0x00	
-	
-/* flat data segment */
-	.word	0xffff, 0x0000		
-	.byte	0x00, 0x93, 0xcf, 0x00	
-
-gdt_end:
-	
-
-/*
- *	When we come here we are in protected mode. We expand 
- *	the stack and copies the data segment from ROM to the
- *	memory.
- *
- *	After that, we call the chipset bootstrap routine that
- *	does what is left of the chipset initialization. 
- *
- *	NOTE aligned to 4 so that we are sure that the prefetch
- *	cache will be reloaded.
- */
-	.align	4
-.globl protected_start
-protected_start:
-
-	lgdt	%cs:gdtptr
-	ljmp	$ROM_CODE_SEG, $__protected_start
-	
-__protected_start:
-	/* Save the BIST value */
-	movl	%eax, %ebp
-
-	intel_chip_post_macro(0x10)	/* post 10 */
-
-	movw	$ROM_DATA_SEG, %ax
-	movw	%ax, %ds
-	movw	%ax, %es
-	movw	%ax, %ss
-	movw	%ax, %fs
-	movw	%ax, %gs
-
-	/* Restore the BIST value to %eax */
-	movl	%ebp, %eax
-
diff --git a/src/cpu/i386/entry32.lds b/src/cpu/i386/entry32.lds
deleted file mode 100644
index 37a75ba6ae..0000000000
--- a/src/cpu/i386/entry32.lds
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
-	_cache_ram_seg_base = DEFINED(CACHE_RAM_BASE)? CACHE_RAM_BASE - _rodata : 0;
-	_cache_ram_seg_base_low    = (_cache_ram_seg_base) & 0xffff;
-	_cache_ram_seg_base_middle = (_cache_ram_seg_base >> 16) & 0xff;
-	_cache_ram_seg_base_high   = (_cache_ram_seg_base >> 24) & 0xff;
-
-	_rom_code_seg_base =  _ltext - _text;
-	_rom_code_seg_base_low    = (_rom_code_seg_base) & 0xffff;
-	_rom_code_seg_base_middle = (_rom_code_seg_base >> 16) & 0xff;
-	_rom_code_seg_base_high   = (_rom_code_seg_base >> 24) & 0xff;
-*/
-
-
-
diff --git a/src/cpu/i386/reset16.inc b/src/cpu/i386/reset16.inc
deleted file mode 100644
index d36c94085e..0000000000
--- a/src/cpu/i386/reset16.inc
+++ /dev/null
@@ -1,21 +0,0 @@
-	.section ".reset"
-	.code16
-.globl	reset_vector
-reset_vector:
-#if _ROMBASE >= 0xffff0000
-	/* jmp _start */
-	.byte  0xe9
-	.int   _start - ( . + 2 )
-	/* Note: The above jump is hand coded to work around bugs in binutils.
-	 * 5 byte are used for a 3 byte instruction.  This works because x86
-	 * is little endian and allows us to use supported 32bit relocations
-	 * instead of the weird 16 bit relocations that binutils does not
-	 * handle consistenly between versions because they are used so rarely.
-	 */
-#else
-# error _ROMBASE is an unsupported value
-#endif
-	. = 0x8;
-	.code32
-	jmp	protected_start
-	.previous
diff --git a/src/cpu/i386/reset16.lds b/src/cpu/i386/reset16.lds
deleted file mode 100644
index 80f2fc0c6f..0000000000
--- a/src/cpu/i386/reset16.lds
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- *      _ROMTOP                 : The top of the rom used where we
- *				  need to put the reset vector.
- */
-
-SECTIONS {
-	_ROMTOP = (_ROMBASE >= 0xffff0000)? 0xfffffff0 : 0xffff0;
-	. = _ROMTOP;
-	.reset . : {
-		*(.reset)
-		. = 15 ;
-		BYTE(0x00);
-	} 
-}
diff --git a/src/cpu/i386/reset32.inc b/src/cpu/i386/reset32.inc
deleted file mode 100644
index 42c68cc770..0000000000
--- a/src/cpu/i386/reset32.inc
+++ /dev/null
@@ -1,10 +0,0 @@
-	.section ".reset"
-	.code16
-.globl	reset_vector
-reset_vector:
-
-	. = 0x8;
-	.code32
-	jmp	protected_start
-
-	.previous
diff --git a/src/cpu/i386/reset32.lds b/src/cpu/i386/reset32.lds
deleted file mode 100644
index fa6db86b1a..0000000000
--- a/src/cpu/i386/reset32.lds
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- *      _ROMTOP                 : The top of the rom used where we
- *				  need to put the reset vector.
- */
-
-SECTIONS {
-	_ROMTOP = _ROMBASE + ROM_IMAGE_SIZE - 0x10;
-	. = _ROMTOP;
-	.reset (.): {
-		*(.reset)
-		. = 15 ;
-		BYTE(0x00);
-	} 
-}