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authorAlexandru Gagniuc <alexandrux.gagniuc@intel.com>2016-02-24 15:08:23 -0800
committerMartin Roth <martinroth@google.com>2016-04-11 16:26:29 +0200
commit0581a6759dea55d21ff7d75da902a608542a4918 (patch)
tree44f469592a73524dea036ddab6b969a938f24454 /src/cpu/dmp
parentb8671eafde839cb93aa4af3888f2fedf59401899 (diff)
soc/intel/apollolake: Implement SPI controller driver
Implement flash read, write, and erase functionality using the hardware sequencing capabilities of the SOC. Due to changes in hardware requirements, the flash chip must be probed differently than on previous platforms (details explained in comments). Note that this is a minimal implementation, and does not provide all the bells and whistles. Change-Id: I6dcc3bc36dfce61927d126d231a16d485acb1bdc Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14246 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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