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authorPratik Prajapati <pratikkumar.v.prajapati@intel.com>2017-08-29 11:38:42 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-01 19:20:58 +0000
commitc8c741d9f9e4d9a91ef5b86a10ece56f8cf98a70 (patch)
tree39d1b15c7665c65b9c62655eb92eacaee0bd08b2 /src/cpu/dmp/vortex86ex
parent9b675796a7407972a60c66ae5f9689f660e12a8e (diff)
soc/intel/cannonlake: Define Max PCIE Root Ports
This patch defines Max PCIE Root Ports and fixes bellow Coverity scan defect, *** CID 1380036: Control flow issues (NO_EFFECT) /src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params() 79 >>> CID 1380036: Control flow issues (NO_EFFECT) >>> "i" is converted to an unsigned type because it's compared to an unsigned constant. 80 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { 81 if (config->PcieRpEnable[i]) 82 mask |= (1 << i); Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/dmp/vortex86ex')
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