cpu/amd/fam10h-fam15h: Set northbridge throttle values

The existing code did not set the northbridge throttle
values on Family 15h, leading to sporadic and random
deadlocks in the crossbar per AMD notes.

Properly set the northbridge throttle values on Family 15h.

Change-Id: I6304b63708c65fedb9c2d46b8c862b7f0adf1102
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12025
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)

2 files changed, 45 insertions, 20 deletions

diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index a421bfcc03..14d8642083 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -860,6 +860,7 @@ static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff)
 		else
 			linktype |= HTPHY_LINKTYPE_UNGANGED;
 	}
+
 	return linktype;
 }
 
@@ -954,26 +955,6 @@ void cpuSetAMDMSR(uint8_t node_id)
 	}
 	AMD_Errata298();
 
-	if (revision & AMD_FAM15_ALL) {
-		uint32_t f5x80;
-		uint8_t enabled;
-		uint8_t compute_unit_count = 0;
-		f5x80 = pci_read_config32(NODE_PCI(node_id, 5), 0x80);
-		enabled = f5x80 & 0xf;
-		if (enabled == 0x1)
-			compute_unit_count = 1;
-		if (enabled == 0x3)
-			compute_unit_count = 2;
-		if (enabled == 0x7)
-			compute_unit_count = 3;
-		if (enabled == 0xf)
-			compute_unit_count = 4;
-		msr = rdmsr(BU_CFG2);
-		msr.lo &= ~(0x3 << 6);				/* ThrottleNbInterface[1:0] */
-		msr.lo |= (((compute_unit_count - 1) & 0x3) << 6);
-		wrmsr(BU_CFG2, msr);
-	}
-
 	/* Revision C0 and above */
 	if (revision & AMD_OR_C0) {
 		uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc);
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index 0a86966537..3bda14c95a 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -132,6 +132,50 @@ static void model_10xxx_init(device_t dev)
 	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
 #endif
 
+	/* Set bus unit configuration */
+	if (is_fam15h()) {
+		uint32_t f5x80;
+		uint8_t enabled;
+		uint8_t compute_unit_count = 0;
+		f5x80 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 5)), 0x80);
+		enabled = f5x80 & 0xf;
+		if (enabled == 0x1)
+			compute_unit_count = 1;
+		if (enabled == 0x3)
+			compute_unit_count = 2;
+		if (enabled == 0x7)
+			compute_unit_count = 3;
+		if (enabled == 0xf)
+			compute_unit_count = 4;
+		msr = rdmsr(BU_CFG2_MSR);
+		msr.lo &= ~(0x3 << 6);				/* ThrottleNbInterface[1:0] */
+		msr.lo |= (((compute_unit_count - 1) & 0x3) << 6);
+		wrmsr(BU_CFG2_MSR, msr);
+	} else {
+		uint32_t f0x60;
+		uint32_t f0x160;
+		uint8_t core_count = 0;
+		uint8_t node_count = 0;
+		f0x60 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x60);
+		core_count = (f0x60 >> 16) & 0x1f;
+		node_count = ((f0x60 >> 4) & 0x7) + 1;
+		if (is_gt_rev_d()) {
+			f0x160 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x160);
+			core_count |= ((f0x160 >> 16) & 0x7) << 5;
+		}
+		core_count++;
+		core_count /= node_count;
+		msr = rdmsr(BU_CFG2_MSR);
+		if (is_gt_rev_d()) {
+			msr.hi &= ~(0x3 << (36 - 32));			/* ThrottleNbInterface[3:2] */
+			msr.hi |= ((((core_count - 1) >> 2) & 0x3) << (36 - 32));
+		}
+		msr.lo &= ~(0x3 << 6);				/* ThrottleNbInterface[1:0] */
+		msr.lo |= (((core_count - 1) & 0x3) << 6);
+		msr.lo &= ~(0x1 << 24);				/* WcPlusDis = 0 */
+		wrmsr(BU_CFG2_MSR, msr);
+	}
+
 	/* Disable Cf8ExtCfg */
 	msr = rdmsr(NB_CFG_MSR);
 	msr.hi &= ~(1 << (46 - 32));