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authorFelix Held <felix-coreboot@felixheld.de>2021-07-13 16:44:18 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-07-14 17:33:34 +0000
commitacbf1541eeedec58ce8a31c6847b2296f40bf4bd (patch)
treefb9ad109c676793801e824707f6f8d0d6c2cc9b1 /src/cpu/amd
parentbf1f1df41ba998a1c3898cd513a47ebdfd05609d (diff)
src: use mca_clear_status function instead of open coding
Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56259 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c8
-rw-r--r--src/cpu/amd/agesa/family15tn/model_15_init.c8
-rw-r--r--src/cpu/amd/agesa/family16kb/model_16_init.c8
-rw-r--r--src/cpu/amd/pi/00730F01/model_16_init.c8
4 files changed, 4 insertions, 28 deletions
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 76c8521761..9539c3deef 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -15,9 +15,7 @@
static void model_14_init(struct device *dev)
{
- u8 i;
msr_t msr;
- unsigned int num_banks;
int msrno;
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
@@ -59,11 +57,7 @@ static void model_14_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 883bd59228..9d4da761c6 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -18,9 +18,7 @@ static void model_15_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");
- u8 i;
msr_t msr;
- unsigned int num_banks;
int msrno;
unsigned int cpu_idx;
#if CONFIG(LOGICAL_CPUS)
@@ -58,11 +56,7 @@ static void model_15_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index f945f80ce1..9fadc7e3e3 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -17,9 +17,7 @@ static void model_16_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 16 Init.\n");
- u8 i;
msr_t msr;
- unsigned int num_banks;
int msrno;
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
@@ -56,11 +54,7 @@ static void model_16_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 3c78c095d0..a5a8064737 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -20,9 +20,7 @@ static void model_16_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 16 Init.\n");
- u8 i;
msr_t msr;
- unsigned int num_banks;
u32 siblings;
/*
@@ -41,11 +39,7 @@ static void model_16_init(struct device *dev)
x86_mtrr_check();
/* zero the machine check error status registers */
- num_banks = mca_get_bank_count();
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC_STATUS(i), msr);
+ mca_clear_status();
/* Enable the local CPU APICs */
setup_lapic();