binaryPI platforms: Drop any ACPI S3 support

No board with binaryPI currently supports HAVE_ACPI_RESUME. For
platforms with PSP the approach is also very different from what
we previously had here.

Furthermore, s3_resume.[ch] files under cpu/amd/pi do not
distinguish between NonVolatile and Volatile buffers of S3 storage.
This means the Volatile buffer that is maintained and available in
CBMEM is unnecessarily copied to SPI flash. This has been fixed on
open-source AGESA directory, so development of S3 suspend support
with binaryPI is better continued with that.

Unfortunately there are further complications and indications that
open-source AGESA may have always had a low-memory corruption
issue. This has to be investigated separately before restoring
or claiming S3 is supported on binaryPI.

Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18501
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

7 files changed, 0 insertions, 363 deletions

diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index afbade4c1a..925c60c100 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -30,7 +30,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
-#include <cpu/amd/pi/s3_resume.h>
 
 static void model_15_init(device_t dev)
 {
@@ -65,9 +64,6 @@ static void model_15_init(device_t dev)
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	if (acpi_is_wakeup())
-		restore_mtrr();
-
 	x86_mtrr_check();
 	x86_enable_cache();
 
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index e252c3d849..c31dec8b03 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -29,7 +29,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
-#include <cpu/amd/pi/s3_resume.h>
 
 #include <amdlib.h>
 #include <PspBaseLib.h>
@@ -80,9 +79,6 @@ static void model_15_init(device_t dev)
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	if (acpi_is_wakeup())
-		restore_mtrr();
-
 	x86_mtrr_check();
 	x86_enable_cache();
 
diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c
index dd1c8e39be..02e5b79e84 100644
--- a/src/cpu/amd/pi/00670F00/model_15_init.c
+++ b/src/cpu/amd/pi/00670F00/model_15_init.c
@@ -29,7 +29,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
-#include <cpu/amd/pi/s3_resume.h>
 
 #include <amdlib.h>
 #include <PspBaseLib.h>
@@ -80,9 +79,6 @@ static void model_15_init(device_t dev)
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	if (acpi_is_wakeup())
-		restore_mtrr();
-
 	x86_mtrr_check();
 	x86_enable_cache();
 
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index a9751a2c2e..294814f149 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -29,7 +29,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam16.h>
 #include <arch/acpi.h>
-#include <cpu/amd/pi/s3_resume.h>
 
 static void model_16_init(device_t dev)
 {
@@ -63,9 +62,6 @@ static void model_16_init(device_t dev)
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	if (acpi_is_wakeup())
-		restore_mtrr();
-
 	x86_mtrr_check();
 	x86_enable_cache();
 
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index 0e31d9fcbb..3dcbbc35c2 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -18,8 +18,6 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
 subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00
 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
 
-romstage-y += s3_resume.c
-ramstage-y += s3_resume.c
 ramstage-$(CONFIG_SPI_FLASH) += spi.c
 
 cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc
@@ -27,18 +25,3 @@ cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc
 romstage-y += heapmanager.c
 ramstage-y += heapmanager.c
 ramstage-y += amd_late_init.c
-
-ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
-
-$(obj)/coreboot_s3nv.rom: $(obj)/config.h
-	echo "    S3 NVRAM   $(CONFIG_S3_DATA_POS) (S3 storage area)"
-	# force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse)
-	printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp
-	mv $@.tmp $@
-
-cbfs-files-y += s3nv
-s3nv-file := $(obj)/coreboot_s3nv.rom
-s3nv-position := $(CONFIG_S3_DATA_POS)
-s3nv-type := raw
-
-endif # CONFIG_HAVE_ACPI_RESUME == y
diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c
deleted file mode 100644
index 338f921ac5..0000000000
--- a/src/cpu/amd/pi/s3_resume.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <AGESA.h>
-#include <Lib/amdlib.h>
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cbmem.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <arch/acpi.h>
-#include <program_loading.h>
-#include <string.h>
-#include "Porting.h"
-#include <northbridge/amd/pi/BiosCallOuts.h>
-#include <halt.h>
-#include "s3_resume.h"
-
-/* The size needs to be 4k aligned, which is the sector size of most flashes. */
-#define S3_DATA_VOLATILE_SIZE		0x6000
-#define S3_DATA_MTRR_SIZE		0x1000
-#define S3_DATA_NONVOLATILE_SIZE	0x1000
-
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
-	(S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE
-#error "Please increase the value of S3_DATA_SIZE"
-#endif
-
-static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
-{
-	/* FIXME: Find file from CBFS. */
-	u32 s3_data = CONFIG_S3_DATA_POS;
-
-	switch (S3DataType) {
-	case S3DataTypeVolatile:
-		*pos = s3_data;
-		*len = S3_DATA_VOLATILE_SIZE;
-		break;
-	case S3DataTypeMTRR:
-		*pos = s3_data + S3_DATA_VOLATILE_SIZE;
-		*len = S3_DATA_MTRR_SIZE;
-		break;
-	case S3DataTypeNonVolatile:
-		*pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE;
-		*len = S3_DATA_NONVOLATILE_SIZE;
-		break;
-	default:
-		*pos = 0;
-		*len = 0;
-		break;
-	}
-}
-
-void restore_mtrr(void)
-{
-	u32 msr;
-	volatile UINT32 *msrPtr;
-	msr_t msr_data;
-
-	printk(BIOS_SPEW, "%s\n", __func__);
-
-	u32 pos, size;
-	get_s3nv_data(S3DataTypeMTRR, &pos, &size);
-	msrPtr = (UINT32 *)(pos + sizeof(UINT32));
-
-	disable_cache();
-
-	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYS_CFG);
-	msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYS_CFG, msr_data);
-
-	/* Now restore the Fixed MTRRs */
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(0x250, msr_data);
-
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(0x258, msr_data);
-
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(0x259, msr_data);
-
-	for (msr = 0x268; msr <= 0x26F; msr++) {
-		msr_data.lo = *msrPtr;
-		msrPtr ++;
-		msr_data.hi = *msrPtr;
-		msrPtr ++;
-		wrmsr(msr, msr_data);
-	}
-
-	/* Disable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYS_CFG);
-	msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYS_CFG, msr_data);
-
-	/* Restore the Variable MTRRs */
-	for (msr = 0x200; msr <= 0x20F; msr++) {
-		msr_data.lo = *msrPtr;
-		msrPtr ++;
-		msr_data.hi = *msrPtr;
-		msrPtr ++;
-		wrmsr(msr, msr_data);
-	}
-
-	/* Restore SYSCFG MTRR */
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(SYS_CFG, msr_data);
-}
-
-#ifdef __PRE_RAM__
-static void move_stack_high_mem(void)
-{
-	uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE,
-		ROMSTAGE_STACK_CBMEM);
-	if (!high_stack)
-		halt();
-
-	/* TODO: Make the switch with empty stack instead. */
-	memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE);
-
-#ifdef __x86_64__
-	__asm__
-	    volatile ("add	%0, %%rsp; add %0, %%rbp; invd"::"g"
-		      (high_stack - BSP_STACK_BASE_ADDR)
-		      :);
-#else
-	__asm__
-	    volatile ("add	%0, %%esp; add %0, %%ebp; invd"::"g"
-		      (high_stack - BSP_STACK_BASE_ADDR)
-		      :);
-#endif
-}
-#endif
-
-#ifndef __PRE_RAM__
-/* FIXME: Why store MTRR in SPI, just use CBMEM ? */
-static u8 mtrr_store[S3_DATA_MTRR_SIZE];
-
-static void write_mtrr(u8 **p_nvram_pos, unsigned idx)
-{
-	msr_t  msr_data;
-	msr_data = rdmsr(idx);
-
-	memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data));
-	*p_nvram_pos += sizeof(msr_data);
-}
-
-void OemAgesaSaveMtrr(void)
-{
-	msr_t  msr_data;
-	u32 i;
-
-	u8 *nvram_pos = (u8 *) mtrr_store;
-
-	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYS_CFG);
-	msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYS_CFG, msr_data);
-
-	/* Fixed MTRRs */
-	write_mtrr(&nvram_pos, 0x250);
-	write_mtrr(&nvram_pos, 0x258);
-	write_mtrr(&nvram_pos, 0x259);
-
-	for (i = 0x268; i < 0x270; i++)
-		write_mtrr(&nvram_pos, i);
-
-	/* Disable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYS_CFG);
-	msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYS_CFG, msr_data);
-
-	/* Variable MTRRs */
-	for (i = 0x200; i < 0x210; i++)
-		write_mtrr(&nvram_pos, i);
-
-	/* SYS_CFG */
-	write_mtrr(&nvram_pos, 0xC0010010);
-	/* TOM */
-	write_mtrr(&nvram_pos, 0xC001001A);
-	/* TOM2 */
-	write_mtrr(&nvram_pos, 0xC001001D);
-
-#if IS_ENABLED(CONFIG_SPI_FLASH)
-	u32 pos, size;
-	get_s3nv_data(S3DataTypeMTRR, &pos, &size);
-	spi_SaveS3info(pos, size, mtrr_store, nvram_pos - (u8 *) mtrr_store);
-#endif
-}
-
-u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
-{
-#if IS_ENABLED(CONFIG_SPI_FLASH)
-	u32 pos, size;
-	get_s3nv_data(S3DataType, &pos, &size);
-	spi_SaveS3info(pos, size, Data, DataSize);
-#endif
-	return AGESA_SUCCESS;
-}
-#endif
-
-void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data)
-{
-	AMD_CONFIG_PARAMS StdHeader;
-
-	u32 pos, size;
-	get_s3nv_data(S3DataType, &pos, &size);
-
-	if (S3DataType == S3DataTypeNonVolatile) {
-		*DataSize = *(UINT32 *) pos;
-		*Data = (void *) (pos + sizeof(UINT32));
-	} else if (S3DataType == S3DataTypeVolatile) {
-		u32 len = *(UINT32 *) pos;
-		void *src = (void *) (pos + sizeof(UINT32));
-		void *dst = (void *) GetHeapBase(&StdHeader);
-		memcpy(dst, src, len);
-		*DataSize = len;
-		*Data = dst;
-	}
-}
-
-#ifdef __PRE_RAM__
-static void set_resume_cache(void)
-{
-	msr_t msr;
-
-	/* disable fixed mtrr for now,  it will be enabled by mtrr restore */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
-	wrmsr(SYSCFG_MSR, msr);
-
-	/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
-	msr.lo = 0 | MTRR_TYPE_WRBACK;
-	msr.hi = 0;
-	wrmsr(MTRR_PHYS_BASE(0), msr);
-	msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
-	msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
-	wrmsr(MTRR_PHYS_MASK(0), msr);
-
-	/* Set the default memory type and disable fixed and enable variable MTRRs */
-	msr.hi = 0;
-	msr.lo = (1 << 11);
-	wrmsr(MTRR_DEF_TYPE_MSR, msr);
-
-	enable_cache();
-}
-
-void prepare_for_resume(void)
-{
-	if (cbmem_recovery(1)) {
-		printk(BIOS_EMERG, "Unable to recover CBMEM\n");
-		halt();
-	}
-
-	post_code(0x62);
-	printk(BIOS_DEBUG, "Move CAR stack.\n");
-	move_stack_high_mem();
-
-	post_code(0x63);
-	disable_cache_as_ram();
-	printk(BIOS_DEBUG, "CAR disabled.\n");
-	set_resume_cache();
-
-}
-#endif
diff --git a/src/cpu/amd/pi/s3_resume.h b/src/cpu/amd/pi/s3_resume.h
deleted file mode 100644
index c23c6621e4..0000000000
--- a/src/cpu/amd/pi/s3_resume.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef S3_RESUME_H
-#define S3_RESUME_H
-
-typedef enum {
-	S3DataTypeNonVolatile=0,	///< NonVolatile Data Type
-	S3DataTypeVolatile,		///< Volatile Data Type
-	S3DataTypeMTRR			///< MTRR storage
-} S3_DATA_TYPE;
-
-void restore_mtrr(void);
-void prepare_for_resume(void);
-
-u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data);
-void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data);
-void OemAgesaSaveMtrr (void);
-
-void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len);
-
-/* This covers node 0 only. */
-#define HIGH_ROMSTAGE_STACK_SIZE	(0x48000 - BSP_STACK_BASE_ADDR)
-
-#endif