cpu/amd: Correct number of MCA banks cleared

Use the value discovered in the MCG_CAP[Count] for the number of MCA
status registers to clear.  The generations should have the following
number of banks:
 * Family 10h: 6 banks
 * Family 12h: 6
 * Family 14h: 6
 * Family 15h: 7
 * Family 16h: 6

Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

8 files changed, 36 insertions, 8 deletions

diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index 93aecadb18..c2f3495eca 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -27,6 +27,8 @@
 #include <cpu/amd/multicore.h>
 #include <cpu/amd/amdfam12.h>
 
+#define MCG_CAP 0x179
+# define MCA_BANKS_MASK 0xff
 #define MC0_STATUS 0x401
 
 static void model_12_init(struct device *dev)
@@ -35,6 +37,7 @@ static void model_12_init(struct device *dev)
 
 	u8 i;
 	msr_t msr;
+	int num_banks;
 
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	u32 siblings;
@@ -52,9 +55,11 @@ static void model_12_init(struct device *dev)
 	disable_cache();
 
 	/* zero the machine check error status registers */
+	msr = rdmsr(MCG_CAP);
+	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
-	for (i = 0; i < 5; i++)
+	for (i = 0; i < num_banks; i++)
 		wrmsr(MC0_STATUS + (i * 4), msr);
 
 	enable_cache();
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index ffb856a9b0..b49d975761 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -28,12 +28,15 @@
 #include <arch/acpi.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
+#define MCG_CAP 0x179
+# define MCA_BANKS_MASK 0xff
 #define MC0_STATUS 0x401
 
 static void model_14_init(struct device *dev)
 {
 	u8 i;
 	msr_t msr;
+	int num_banks;
 	int msrno;
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	u32 siblings;
@@ -75,9 +78,11 @@ static void model_14_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
+	msr = rdmsr(MCG_CAP);
+	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
-	for (i = 0; i < 6; i++)
+	for (i = 0; i < num_banks; i++)
 		wrmsr(MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 8ae184e78d..fdcb9a2332 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -35,6 +35,7 @@ static void model_15_init(struct device *dev)
 
 	u8 i;
 	msr_t msr;
+	int num_banks;
 	int msrno;
 	unsigned int cpu_idx;
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
@@ -72,9 +73,11 @@ static void model_15_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
+	msr = rdmsr(MCG_CAP);
+	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
-	for (i = 0; i < 6; i++)
+	for (i = 0; i < num_banks; i++)
 		wrmsr(MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index 92c7bcaee2..1b5db23ff5 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -34,6 +34,7 @@ static void model_16_init(struct device *dev)
 
 	u8 i;
 	msr_t msr;
+	int num_banks;
 	int msrno;
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	u32 siblings;
@@ -70,9 +71,11 @@ static void model_16_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
+	msr = rdmsr(MCG_CAP);
+	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
-	for (i = 0; i < 6; i++)
+	for (i = 0; i < num_banks; i++)
 		wrmsr(MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index 74d4673bc0..58364d4cac 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -62,6 +62,7 @@ static void model_10xxx_init(struct device *dev)
 {
 	u8 i;
 	msr_t msr;
+	int num_banks;
 	struct node_core_id id;
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	u32 siblings;
@@ -109,9 +110,11 @@ static void model_10xxx_init(struct device *dev)
 	disable_cache();
 
 	/* zero the machine check error status registers */
+	msr = rdmsr(MCG_CAP);
+	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
-	for (i = 0; i < 5; i++)
+	for (i = 0; i < num_banks; i++)
 		wrmsr(MC0_STATUS + (i * 4), msr);
 
 	enable_cache();
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index 592ca4f086..0269a1e260 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -35,6 +35,7 @@ static void model_15_init(struct device *dev)
 
 	u8 i;
 	msr_t msr;
+	int num_banks;
 	int msrno;
 	unsigned int cpu_idx;
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
@@ -69,9 +70,11 @@ static void model_15_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
+	msr = rdmsr(MCG_CAP);
+	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
-	for (i = 0; i < 6; i++)
+	for (i = 0; i < num_banks; i++)
 		wrmsr(MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index 0540a72fad..424a6c06ff 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -51,6 +51,7 @@ static void model_15_init(struct device *dev)
 
 	u8 i;
 	msr_t msr;
+	int num_banks;
 	int msrno;
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	u32 siblings;
@@ -81,9 +82,11 @@ static void model_15_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
+	msr = rdmsr(MCG_CAP);
+	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
-	for (i = 0; i < 6; i++)
+	for (i = 0; i < num_banks; i++)
 		wrmsr(MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 3ae841d0b1..1f2c30fd03 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -34,6 +34,7 @@ static void model_16_init(struct device *dev)
 
 	u8 i;
 	msr_t msr;
+	int num_banks;
 	int msrno;
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	u32 siblings;
@@ -66,9 +67,11 @@ static void model_16_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
+	msr = rdmsr(MCG_CAP);
+	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
-	for (i = 0; i < 6; i++)
+	for (i = 0; i < num_banks; i++)
 		wrmsr(MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */