diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-08 22:14:59 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-11-22 23:10:53 +0100 |
| commit | baa1acde7bb46a06e34404796aeaa1d5c7c6ec47 (patch) | |
| tree | 025b311e7c00f3823029605ceec111ca437997e3 /src/cpu/amd | |
| parent | aab3ad256a58a9b77ebd3e8ed6e4c4c700c1c9da (diff) | |
cpu/amd/fam10h15h: Set up SRI to XCS Token Count registers on Family 15h
Change-Id: Ic992efad11d8e231ec85c793cf1e478bea0b9d3e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12040
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/init_cpus.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 34a67da750..439e4fa1a5 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -1489,6 +1489,46 @@ static void cpuSetAMDPCI(u8 node) pci_write_config32(NODE_PCI(node, 3), (link << 2) + 0x148, dword); } } + + /* Set up the SRI to XCS Token Count */ + uint8_t free_tok; + uint8_t up_rsp_tok; + + /* Set defaults */ + free_tok = 0xa; + up_rsp_tok = 0x3; + + if (!dual_node) { + free_tok = 0xa; + up_rsp_tok = 0x3; + } else { + if ((sockets == 1) + || ((sockets == 2) && (sockets_populated == 1))) { + if (probe_filter_enabled) { + free_tok = 0x9; + up_rsp_tok = 0x3; + } else { + free_tok = 0xa; + up_rsp_tok = 0x3; + } + } else if ((sockets == 2) && (sockets_populated == 2)) { + free_tok = 0xb; + up_rsp_tok = 0x1; + } else if ((sockets == 4) && (sockets_populated == 2)) { + free_tok = 0xa; + up_rsp_tok = 0x3; + } else if ((sockets == 4) && (sockets_populated == 4)) { + free_tok = 0x9; + up_rsp_tok = 0x1; + } + } + + dword = pci_read_config32(NODE_PCI(node, 3), 0x140); + dword &= ~(0xf << 20); /* FreeTok = free_tok */ + dword |= ((free_tok & 0xf) << 20); + dword &= ~(0x3 << 8); /* UpRspTok = up_rsp_tok */ + dword |= ((up_rsp_tok & 0x3) << 8); + pci_write_config32(NODE_PCI(node, 3), 0x140, dword); } printk(BIOS_DEBUG, " done\n"); |