diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-06-18 09:10:53 +0300 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-07-03 09:46:50 +0200 |
commit | e1b468e1a7cbea55108fb106105612e1f50c9487 (patch) | |
tree | 91d79aab170c0112595a2c073187affa36c6b4bc /src/cpu/amd | |
parent | adf3d6ff52eb674267eacbf37f811c7144e857b3 (diff) |
AGESA boards: Use acpi_s3_resume_allowed()
This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the
build of romstage also for boards without HAVE_ACPI_RESUME.
These symbols got exposed as the use of preprocessor directives was
reduced.
We expect the linker to do a fair job and optimize away function
bodies that are on unreachable execution paths.
Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6067
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r-- | src/cpu/amd/agesa/Kconfig | 1 | ||||
-rw-r--r-- | src/cpu/amd/agesa/Makefile.inc | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index b53e4b0fee..e982a83770 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -32,6 +32,7 @@ config CPU_AMD_AGESA select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER + select BROKEN_CAR_MIGRATE select SPI_FLASH if HAVE_ACPI_RESUME if CPU_AMD_AGESA diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index d6d2f247d6..1f2966458b 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -23,8 +23,8 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb -romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +romstage-y += s3_resume.c +ramstage-y += s3_resume.c ramstage-$(CONFIG_SPI_FLASH) += spi.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc |