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authorzbao <fishbaozi@gmail.com>2012-04-05 13:20:50 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-04-12 00:17:35 +0200
commit392562263858011ef898e377477124f5f66b1302 (patch)
tree8ac8b9437dbfb6f5f56af42f0163a006b0f745e8 /src/cpu/amd
parent9bcdbf8eaa0c73d130ba555163f89fa1759c8c99 (diff)
S3 code in vendorcode folder.
Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/agesa/family14/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
index 774d401b63..b08ceebf80 100644
--- a/src/cpu/amd/agesa/family14/Makefile.inc
+++ b/src/cpu/amd/agesa/family14/Makefile.inc
@@ -113,6 +113,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c