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authorQingPei Wang <wangqingpei@gmail.com>2011-09-13 18:04:22 +0800
committerPeter Stuge <peter@stuge.se>2011-09-24 15:58:12 +0200
commit8eb4273290ea577d06282d350e3fe884145c4288 (patch)
treea6c6b4903c4be764cef226574e70444dc6ab824a /src/cpu/amd
parent62ff00e13f3fb349bb8ce3065f6915448bfd875e (diff)
Add AMD Family 10h PH-E0 support
the patch file comes from src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE /F10MicrocodePatch010000bf.c Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802 Signed-off-by: QingPei Wang <wangqingpei@gmail.com> Reviewed-on: http://review.coreboot.org/202 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src/cpu/amd')
-rw-r--r--src/cpu/amd/model_10xxx/mc_patch_010000bf.h164
-rw-r--r--src/cpu/amd/model_10xxx/model_10xxx_init.c1
-rw-r--r--src/cpu/amd/model_10xxx/update_microcode.c2
3 files changed, 167 insertions, 0 deletions
diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000bf.h b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h
new file mode 100644
index 0000000000..9baaa9bfdd
--- /dev/null
+++ b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h
@@ -0,0 +1,164 @@
+/*
+ ============================================================
+ Copyright (c) Advanced Micro Devices, Inc., 2004-2008
+
+ The enclosed microcode is intended to be used with AMD
+ Microprocessors. You may copy, view and install the
+ enclosed microcode only for development and deployment of
+ firmware, BIOS, or operating system code for computer
+ systems that contain AMD processors. You are not
+ authorized to use the enclosed microcode for any other
+ purpose.
+
+ THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR
+ IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO
+ WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT,
+ TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES
+ ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ AMD does not assume any responsibility for any errors which
+ may appear in this microcode or any other related
+ information provided to you by AMD, or result from use of
+ this microcode. AMD is not obligated to furnish, support,
+ or make any further information, software, technical
+ information, know-how, or show-how available related to this
+ microcode.
+
+ The microcode is provided with "RESTRICTED RIGHTS." Use,
+ duplication, or disclosure by the U.S. Government is subject
+ to the restrictions as set forth in FAR 52.227-14 and
+ DFAR252.227-7013, et seq., or its successor. Use of the
+ microcode by the U.S. Government constitutes
+ acknowledgement of AMD's proprietary rights in them.
+ ============================================================
+*/
+
+
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+0x42, 0x82, 0x02, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
+0x00, 0xff, 0xdf, 0x03, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00,
+0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
+0xf0, 0x6f, 0xf8, 0x07, 0x01, 0x80, 0xff, 0xef, 0x7f, 0xbf, 0xff, 0x81,
+0xdf, 0x95, 0xc1, 0xaf, 0xff, 0x91, 0xfc, 0x2f, 0x48, 0x57, 0x06, 0xbf,
+0xff, 0x4f, 0xb0, 0xff, 0x32, 0xd8, 0x3a, 0xfc, 0xd7, 0x00, 0x40, 0x95,
+0x81, 0xff, 0x94, 0x01, 0x1f, 0xe0, 0xe7, 0xe1, 0xff, 0xff, 0x53, 0xce,
+0x7f, 0xa9, 0xeb, 0x83, 0xff, 0xef, 0x4b, 0xfd, 0xfc, 0xbd, 0xbd, 0x0e,
+0xff, 0x7b, 0x00, 0xe0, 0x9c, 0x56, 0x0e, 0x00, 0xd0, 0x0f, 0xe0, 0x73,
+0xff, 0x81, 0x7f, 0x00, 0xc3, 0x3f, 0x80, 0x7f, 0xfc, 0x07, 0xfe, 0x01,
+0x0d, 0xff, 0x00, 0xfe, 0xe0, 0xfd, 0x35, 0x00, 0xe0, 0x0d, 0x2b, 0x07,
+0x3a, 0xf0, 0x07, 0xf4, 0x96, 0xff, 0xed, 0x3f, 0xff, 0xe1, 0x1f, 0xab,
+0x5b, 0x02, 0x00, 0xfe, 0xfb, 0x87, 0x7f, 0xac, 0x00, 0xa8, 0xcd, 0x1a,
+0x6f, 0x72, 0xc0, 0xff, 0xfc, 0x3c, 0xfc, 0x03, 0x1f, 0xc0, 0x7f, 0xe0,
+0xe0, 0xdf, 0xf0, 0x0f, 0x7f, 0x00, 0xff, 0x81, 0x80, 0x7f, 0xc3, 0x3f,
+0x0f, 0x00, 0xfc, 0x7f, 0xff, 0x7f, 0x79, 0xfc, 0x01, 0x7e, 0x1e, 0xfe,
+0x2b, 0x07, 0xe0, 0xfe, 0x07, 0xf0, 0x39, 0xe8, 0xc0, 0x3f, 0x80, 0xff,
+0x1f, 0xc0, 0xbf, 0xe1, 0xb9, 0x06, 0x00, 0x78, 0xf6, 0xff, 0xbf, 0x80,
+0xff, 0x00, 0x3f, 0x0f, 0xff, 0xff, 0x8f, 0xe2, 0xfc, 0x03, 0xfc, 0x3c,
+0x7f, 0x34, 0x1e, 0xf0, 0xd0, 0xef, 0xe5, 0xf3, 0xff, 0xdf, 0x03, 0x00,
+0xee, 0xa3, 0x72, 0x00, 0x83, 0x7e, 0x00, 0x9f, 0xf8, 0xfd, 0xff, 0x07,
+0x1f, 0xbe, 0xb1, 0xec, 0x65, 0x97, 0xff, 0x1f, 0x79, 0xf8, 0x07, 0xf8,
+0x80, 0xc4, 0x97, 0x01, 0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80,
+0x01, 0xfc, 0x07, 0xfe, 0xfe, 0x0d, 0xff, 0x00, 0x07, 0xf0, 0x1f, 0xf8,
+0xf8, 0x37, 0xfc, 0x03, 0x00, 0xc0, 0xff, 0xf7, 0x3f, 0x80, 0xff, 0xc0,
+0xc0, 0xbf, 0xe1, 0x1f, 0xff, 0x00, 0xfe, 0x03, 0x00, 0xff, 0x86, 0x7f,
+0xfc, 0x03, 0xf8, 0x0f, 0x01, 0xfc, 0x1b, 0xfe, 0x7b, 0x00, 0xe0, 0xff,
+0xe0, 0x1f, 0xc0, 0x7f, 0x0f, 0xe0, 0xdf, 0xf0, 0x81, 0x7f, 0x00, 0xff,
+0x3f, 0x80, 0x7f, 0xc3, 0x07, 0xfe, 0x01, 0xfc, 0xff, 0x00, 0xfe, 0x0d,
+0xff, 0x3d, 0x00, 0xf0, 0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f,
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+0x86, 0x7f, 0x00, 0xff, 0xf8, 0xff, 0x1e, 0x00, 0xf0, 0x1f, 0xf8, 0x07,
+0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x7f, 0xe0, 0x1f, 0xdf, 0xf0, 0x0f, 0xe0,
+0x00, 0xff, 0x81, 0x7f, 0x7f, 0xc3, 0x3f, 0x80, 0x00, 0xfc, 0x7f, 0x0f,
+0x03, 0xf8, 0x0f, 0xfc, 0xfc, 0x1b, 0xfe, 0x01, 0x0f, 0xe0, 0x3f, 0xf0,
+0xf0, 0x6f, 0xf8, 0x07, 0x3f, 0x80, 0xff, 0xc0, 0xc0, 0xbf, 0xe1, 0x1f,
+0x07, 0x00, 0xfe, 0xbf, 0xfe, 0x01, 0xfc, 0x07, 0x00, 0xfe, 0x0d, 0xff,
+0xf8, 0x07, 0xf0, 0x1f, 0x03, 0xf8, 0x37, 0xfc, 0xe0, 0x1f, 0xc0, 0x7f,
+0x0f, 0xe0, 0xdf, 0xf0, 0xdf, 0x03, 0x00, 0xff, 0x03, 0xff, 0x00, 0xfe,
+0x7f, 0x00, 0xff, 0x86, 0x0f, 0xfc, 0x03, 0xf8, 0xfe, 0x01, 0xfc, 0x1b,
+0x3f, 0xf0, 0x0f, 0xe0, 0xf8, 0x07, 0xf0, 0x6f, 0xff, 0xef, 0x01, 0x80,
+
+
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+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 2e8bbfe09d..cf11135671 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -157,6 +157,7 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
{ X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
{ X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */
+ { X86_VENDOR_AMD, 0x100FA0 }, /* PH-E0 */
{ 0, 0 },
};
diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c
index fa3b4f8a72..a9faafa470 100644
--- a/src/cpu/amd/model_10xxx/update_microcode.c
+++ b/src/cpu/amd/model_10xxx/update_microcode.c
@@ -51,6 +51,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
* 00100F62h (DA-C2) 1062h 0100009Fh
* 00100F63h (DA-C3) 1043h 010000b6h
* 00100F81h (HY-D1) 1081h 010000c4h
+ * 00100FA0h (PH-E0) 10A0h 010000bfh
*/
#include CONFIG_AMD_UCODE_PATCH_FILE
@@ -78,6 +79,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) {
0x100f62, 0x1062,
0x100f63, 0x1043,
0x100f81, 0x1081,
+ 0x100fa0, 0x10A0,
};
u32 new_id;