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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-09-05 17:50:29 -0500
committerJonathan A. Kollasch <jakllsch@kollasch.net>2015-10-24 21:33:07 +0200
commit1c4508e77c32e2db7ecba49fe92159242d831f56 (patch)
treed2b88b87c525a24b02455850245858202016df11 /src/cpu/amd/socket_G34
parent1fec04b47e3ebcde3a1b34b81120e3b83c88f323 (diff)
cpu/amd: Add initial support for AMD Socket G34 processors
Change-Id: Iccd034f32c26513edd52ca3a11a30f61c362682d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11940 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/cpu/amd/socket_G34')
-rw-r--r--src/cpu/amd/socket_G34/Kconfig29
-rw-r--r--src/cpu/amd/socket_G34/Makefile.inc14
-rw-r--r--src/cpu/amd/socket_G34/socket_G34.c25
3 files changed, 68 insertions, 0 deletions
diff --git a/src/cpu/amd/socket_G34/Kconfig b/src/cpu/amd/socket_G34/Kconfig
new file mode 100644
index 0000000000..abc9726c78
--- /dev/null
+++ b/src/cpu/amd/socket_G34/Kconfig
@@ -0,0 +1,29 @@
+config CPU_AMD_SOCKET_G34_NON_AGESA
+ bool
+ select CPU_AMD_MODEL_10XXX
+ select PCI_IO_CFG_EXT
+ select X86_AMD_FIXED_MTRRS
+
+if CPU_AMD_SOCKET_G34_NON_AGESA
+
+config CPU_SOCKET_TYPE
+ hex
+ default 0x15
+
+config EXT_RT_TBL_SUPPORT
+ bool
+ default n
+
+config CBB
+ hex
+ default 0x0
+
+config CDB
+ hex
+ default 0x18
+
+config XIP_ROM_SIZE
+ hex
+ default 0x80000
+
+endif
diff --git a/src/cpu/amd/socket_G34/Makefile.inc b/src/cpu/amd/socket_G34/Makefile.inc
new file mode 100644
index 0000000000..a8e1333d9b
--- /dev/null
+++ b/src/cpu/amd/socket_G34/Makefile.inc
@@ -0,0 +1,14 @@
+ramstage-y += socket_G34.c
+subdirs-y += ../model_10xxx
+subdirs-y += ../quadcore
+subdirs-y += ../mtrr
+subdirs-y += ../microcode
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/pae
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/smm
+subdirs-y += ../smm
+
+cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_G34/socket_G34.c b/src/cpu/amd/socket_G34/socket_G34.c
new file mode 100644
index 0000000000..90f7b8c44f
--- /dev/null
+++ b/src/cpu/amd/socket_G34/socket_G34.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations cpu_amd_socket_G34_ops = {
+ CHIP_NAME("socket G34")
+};