diff options
| author | Dhaval Sharma <dhaval.v.sharma@intel.com> | 2015-08-27 17:13:19 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:35:37 +0000 |
| commit | 9ae6cd4280f0ff02711726393b74ca119fb1fc92 (patch) | |
| tree | 33de79a75b354a4dfa9ecce9d20fea4520c890ff /src/cpu/amd/socket_F | |
| parent | 0c66e866c95758c0e5557581a3af2cef4743c4ff (diff) | |
Skylake:Set DISB inside romstage after mrc init
Set DISB inside romstage right after successful mrc init such that
any reset events afterwards can take fast boot path and in turn
achieve better boot performance
BRANCH=NONE
BUG=chrome-os-partner:43637
TEST=Built for kunimitsu and tested DISB is set correctly and fast
boot path is taken.
Change-Id: I230ff76287f90c5d3655a77bbaca666af37c4aae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7bdc6900012c99187bb90904df18c2b3f9e52c61
Original-Change-Id: Ie08b4a4f29a7c5cb47e508bc59a5e95f8e36fa00
Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295509
Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11550
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd/socket_F')
0 files changed, 0 insertions, 0 deletions