diff options
| author | Damien Zammit <damien@zamaudio.com> | 2016-11-28 00:29:10 +1100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-04 18:56:01 +0100 |
| commit | 75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7 (patch) | |
| tree | 618c2bc04f44cf73d3dae288bff0a5e2ef44d616 /src/cpu/amd/quadcore | |
| parent | 6c20b65849aeda664cc40ebc0f0bab2e99768423 (diff) | |
amdfam10: Perform major include ".c" cleanup
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Diffstat (limited to 'src/cpu/amd/quadcore')
| -rw-r--r-- | src/cpu/amd/quadcore/quadcore.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 3ca7f3e0e7..2f0822e4b9 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -16,18 +16,13 @@ #include <console/console.h> #include <pc80/mc146818rtc.h> -#include <northbridge/amd/amdht/ht_wrapper.c> #if CONFIG_HAVE_OPTION_TABLE #include "option_table.h" #endif #include "cpu/amd/quadcore/quadcore_id.c" -/* get_boot_apic_id and wait_cpu_state located in init_cpus.c */ -uint32_t get_boot_apic_id(uint8_t node, uint32_t core); -uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2); - -static u32 get_core_num_in_bsp(u32 nodeid) +u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; if (is_fam15h()) { @@ -46,7 +41,7 @@ static u32 get_core_num_in_bsp(u32 nodeid) return dword; } -static u8 set_apicid_cpuid_lo(void) +u8 set_apicid_cpuid_lo(void) { // set the NB_CFG[54]=1; why the OS will be happy with that ??? msr_t msr; @@ -57,7 +52,7 @@ static u8 set_apicid_cpuid_lo(void) return 1; } -static void real_start_other_core(uint32_t nodeid, uint32_t cores) +void real_start_other_core(uint32_t nodeid, uint32_t cores) { ssize_t i; uint32_t dword; |