diff options
author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/cpu/amd/pi | |
parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/amd/pi')
-rw-r--r-- | src/cpu/amd/pi/00630F01/fixme.c | 2 | ||||
-rw-r--r-- | src/cpu/amd/pi/00630F01/model_15_init.c | 6 | ||||
-rw-r--r-- | src/cpu/amd/pi/00660F01/fixme.c | 2 | ||||
-rw-r--r-- | src/cpu/amd/pi/00660F01/model_15_init.c | 4 | ||||
-rw-r--r-- | src/cpu/amd/pi/00730F01/fixme.c | 2 | ||||
-rw-r--r-- | src/cpu/amd/pi/00730F01/model_16_init.c | 4 |
6 files changed, 10 insertions, 10 deletions
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index ae2a2dfe88..10fd9f568c 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -88,7 +88,7 @@ void amd_initmmio(void) MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + if (CONFIG(UDELAY_LAPIC)){ LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 5455b0cf11..3a641bf07f 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -36,7 +36,7 @@ static void model_15_init(struct device *dev) int num_banks; int msrno; unsigned int cpu_idx; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) u32 siblings; #endif @@ -78,7 +78,7 @@ static void model_15_init(struct device *dev) /* Enable the local CPU APICs */ setup_lapic(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { @@ -98,7 +98,7 @@ static void model_15_init(struct device *dev) msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (CONFIG(HAVE_SMI_HANDLER)) { cpu_idx = cpu_info()->index; printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index e028b6f85b..2cbeab8316 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -94,7 +94,7 @@ void amd_initmmio(void) MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { + if (CONFIG(UDELAY_LAPIC)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index d156525b60..65d87c22ec 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -51,7 +51,7 @@ static void model_15_init(struct device *dev) msr_t msr; int num_banks; int msrno; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) u32 siblings; #endif @@ -90,7 +90,7 @@ static void model_15_init(struct device *dev) /* Enable the local CPU APICs */ setup_lapic(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 163066b6d8..3769319866 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -99,7 +99,7 @@ void amd_initmmio(void) MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { + if (CONFIG(UDELAY_LAPIC)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); MsrReg |= 1 << 11; LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 7ae89b48e8..5678c5f58d 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -34,7 +34,7 @@ static void model_16_init(struct device *dev) msr_t msr; int num_banks; int msrno; -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) u32 siblings; #endif @@ -75,7 +75,7 @@ static void model_16_init(struct device *dev) /* Enable the local CPU APICs */ setup_lapic(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { |