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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-04-13 15:25:43 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-07-17 19:31:09 +0000 |
commit | bebd766f165e7b3e1f6776c52067ab8998422607 (patch) | |
tree | 65a5c5e921a79af38b93154a85c274171056c402 /src/cpu/amd/pi/romstage.c | |
parent | 9de82612fe722cf3526ed508a463bfb6c9f911d0 (diff) |
binaryPI: Disable CAR with empty stack
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
While we still preserve cache contents (there is wbinvd deep
inside AMD_DISABLE_STACK macro), we now actually do a stack
switch and much more closely meet the specification of CAR
teardown sequence in AGESA specifications.
We now somewhat incorrectly include files from agesa/ tree,
but the whole agesawrapper.c file removal will address the
issue of overall directory layout.
Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd/pi/romstage.c')
-rw-r--r-- | src/cpu/amd/pi/romstage.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c new file mode 100644 index 0000000000..393cbd4aeb --- /dev/null +++ b/src/cpu/amd/pi/romstage.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <cpu/amd/car.h> +#include <cpu/x86/mtrr.h> +#include <console/console.h> +#include <program_loading.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <northbridge/amd/agesa/state_machine.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +void * asmlinkage romstage_main(unsigned long bist) +{ + uintptr_t stack_top = CACHE_TMP_RAMTOP; + u8 initial_apic_id = cpuid_ebx(1) >> 24; + + /* Only BSP returns from here. */ + cache_as_ram_main(bist, initial_apic_id); + + printk(BIOS_DEBUG, "Move CAR stack.\n"); + return (void*)stack_top; +} + +void asmlinkage romstage_after_car(void) +{ + printk(BIOS_DEBUG, "CAR disabled.\n"); + + agesa_postcar(NULL); + + run_ramstage(); +} |