diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/cpu/amd/pi/00660F01/model_15_init.c | |
parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/cpu/amd/pi/00660F01/model_15_init.c')
-rw-r--r-- | src/cpu/amd/pi/00660F01/model_15_init.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 424a6c06ff..3f3a1fda44 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -15,6 +15,8 @@ #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <device/device.h> #include <device/pci.h> @@ -24,8 +26,6 @@ #include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/amdfam15.h> #include <arch/acpi.h> #include <amdlib.h> @@ -82,12 +82,12 @@ static void model_15_init(struct device *dev) x86_enable_cache(); /* zero the machine check error status registers */ - msr = rdmsr(MCG_CAP); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); |