diff options
author | Evelyn Huang <evhuang@google.com> | 2017-06-07 12:31:44 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-06-12 04:11:43 +0200 |
commit | 877b5866916a50734a7a1bc1a0696610536eb8d8 (patch) | |
tree | 5ba87546a6cf3f797b3a59e3148a597644b74836 /src/cpu/amd/pi/00630F01/model_15_init.c | |
parent | 53de6cd1c3597f38b69509ea5a34f61c71ca1f5d (diff) |
src/cpu/amd/pi/00630F01 Fix checkpatch warnings and errors
Fix space prohibited between function name and open parenthesis, line
over 80 characters, unnecessary braces for single statement blocks,
space required before open brace errors and warnings
Change-Id: I66f1a8640ec5c9d8a1dd039088598f40e8d30f95
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/amd/pi/00630F01/model_15_init.c')
-rw-r--r-- | src/cpu/amd/pi/00630F01/model_15_init.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 925c60c100..c2f2e9d39e 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -43,21 +43,24 @@ static void model_15_init(device_t dev) u32 siblings; #endif - disable_cache (); + disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs + /* + * BSP: make a0000-bffff UC, c0000-fffff WB, + * same as OntarioApMtrrSettingsList for APs + */ msr.lo = msr.hi = 0; - wrmsr (0x259, msr); + wrmsr(0x259, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); + wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; @@ -70,10 +73,8 @@ static void model_15_init(device_t dev) /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < 6; i++) wrmsr(MCI_STATUS + (i * 4), msr); - } - /* Enable the local CPU APICs */ setup_lapic(); |