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authorStefan Reinauer <stepan@coresystems.de>2009-06-30 15:17:49 +0000
committerStefan Reinauer <stepan@openbios.org>2009-06-30 15:17:49 +0000
commit0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch)
tree81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/cpu/amd/mtrr
parent9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff)
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/mtrr')
-rw-r--r--src/cpu/amd/mtrr/amd_earlymtrr.c4
-rw-r--r--src/cpu/amd/mtrr/amd_mtrr.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/amd/mtrr/amd_earlymtrr.c b/src/cpu/amd/mtrr/amd_earlymtrr.c
index 948d4ac83b..c633c957f0 100644
--- a/src/cpu/amd/mtrr/amd_earlymtrr.c
+++ b/src/cpu/amd/mtrr/amd_earlymtrr.c
@@ -41,11 +41,11 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs)
msr.lo = (((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK);
wrmsr(TOP_MEM, msr);
-#if defined(XIP_ROM_SIZE)
+#if defined(CONFIG_XIP_ROM_SIZE)
/* enable write through caching so we can do execute in place
* on the flash rom.
*/
- set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
+ set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
#endif
/* Set the default memory type and enable fixed and variable MTRRs
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index e8e9273868..3d72fe684e 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -180,7 +180,7 @@ void amd_setup_mtrrs(void)
/* FIXME we should probably query the cpu for this
* but so far this is all any recent AMD cpu has supported.
*/
- address_bits = CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
+ address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
/* Now that I have mapped what is memory and what is not
* Setup the mtrrs so we can cache the memory.