diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2013-07-08 16:23:54 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-11 22:36:59 +0200 |
| commit | 4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c (patch) | |
| tree | 6bd8440a05f6ea1184c0a5500d43cc92ab683f01 /src/cpu/amd/mtrr | |
| parent | 0cb07e3476d9408d0935253f9f26c0a8ddc28401 (diff) | |
cpu: Fix spelling
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/mtrr')
| -rw-r--r-- | src/cpu/amd/mtrr/amd_mtrr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 2f3e6e340f..033ec53d3a 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -128,10 +128,10 @@ void amd_setup_mtrrs(void) } /* Now that I have mapped what is memory and what is not - * Setup the mtrrs so we can cache the memory. + * Set up the mtrrs so we can cache the memory. */ - // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and dont need + // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need // variable MTRR to span memory above 4GB // Lower revisions K8 need variable MTRR over 4GB x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1); |