diff options
| author | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 20:46:15 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 20:46:15 +0000 |
| commit | d4b278c02c1da92219ebeb34204b9768934aeca3 (patch) | |
| tree | 488d097cac9744cfc9b8ff7c89ce69bcb21370cb /src/cpu/amd/mtrr | |
| parent | 2e3757d11c565a8fe68dc2a2c34975e98304533c (diff) | |
AMD Rev F support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/mtrr')
| -rw-r--r-- | src/cpu/amd/mtrr/amd_earlymtrr.c | 1 | ||||
| -rw-r--r-- | src/cpu/amd/mtrr/amd_mtrr.c | 4 |
2 files changed, 2 insertions, 3 deletions
diff --git a/src/cpu/amd/mtrr/amd_earlymtrr.c b/src/cpu/amd/mtrr/amd_earlymtrr.c index f2de79102b..948d4ac83b 100644 --- a/src/cpu/amd/mtrr/amd_earlymtrr.c +++ b/src/cpu/amd/mtrr/amd_earlymtrr.c @@ -15,7 +15,6 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs) */ msr_t msr; const unsigned long *msr_addr; - unsigned long cr0; #if 0 /* Enable the access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index b422f9f425..e8e9273868 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -149,7 +149,7 @@ void amd_setup_mtrrs(void) msr.lo = state.mmio_basek << 10; wrmsr(TOP_MEM, msr); - if(state.tomk>(4*1024*1024)) { + if(state.tomk > (4*1024*1024)) { /* Setup TOP_MEM2 */ msr.hi = state.tomk >> 22; msr.lo = state.tomk << 10; @@ -180,7 +180,7 @@ void amd_setup_mtrrs(void) /* FIXME we should probably query the cpu for this * but so far this is all any recent AMD cpu has supported. */ - address_bits = 40; + address_bits = CPU_ADDR_BITS; //K8 could be 40, and GH could be 48 /* Now that I have mapped what is memory and what is not * Setup the mtrrs so we can cache the memory. |