AMD Geode cpus: apply un-written naming rules

Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.

Rename directories and Kconfig as follows:
   model_lx  -> geode_lx
   model_gx1 -> geode_gx1
   model_gx2 -> geode_gx2

Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/613
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 files changed, 0 insertions, 824 deletions

diff --git a/src/cpu/amd/model_lx/Kconfig b/src/cpu/amd/model_lx/Kconfig
deleted file mode 100644
index 742ef6911a..0000000000
--- a/src/cpu/amd/model_lx/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-config CPU_AMD_LX
-	bool
-
-if CPU_AMD_LX
-
-config CPU_SPECIFIC_OPTIONS
-	def_bool y
-	select CACHE_AS_RAM
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xc8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
-config GEODE_VSA
-	bool
-	default y
-	select PCI_OPTION_ROM_RUN_REALMODE
-
-config GEODE_VSA_FILE
-	bool "Add a VSA image"
-	help
-	  Select this option if you have an AMD Geode LX vsa that you would
-	  like to add to your ROM.
-
-	  You will be able to specify the location and file name of the
-	  image later.
-
-config VSA_FILENAME
-	string "AMD Geode LX VSA path and filename"
-	depends on GEODE_VSA_FILE
-	default "gpl_vsa_lx_102.bin"
-	help
-	  The path and filename of the file to use as VSA.
-
-endif # CPU_AMD_LX
diff --git a/src/cpu/amd/model_lx/Makefile.inc b/src/cpu/amd/model_lx/Makefile.inc
deleted file mode 100644
index 3455d1e5d6..0000000000
--- a/src/cpu/amd/model_lx/Makefile.inc
+++ /dev/null
@@ -1,9 +0,0 @@
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
-
-driver-y += model_lx_init.c
-ramstage-y += cpubug.c
-
-cpu_incs += $(src)/cpu/amd/model_lx/cache_as_ram.inc
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc
deleted file mode 100644
index a1d775d6d6..0000000000
--- a/src/cpu/amd/model_lx/cache_as_ram.inc
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#define	LX_STACK_BASE		CONFIG_DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
-#define	LX_STACK_END		LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
-
-#define	LX_NUM_CACHELINES	0x080	/* there are 128lines per way */
-#define	LX_CACHELINE_SIZE	0x020	/* there are 32bytes per line */
-#define	LX_CACHEWAY_SIZE	(LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
-#define	CR0_CD				0x40000000	/* bit 30 = Cache Disable */
-#define	CR0_NW				0x20000000	/* bit 29 = Not Write Through */
-#include <cpu/amd/lxdef.h>
-#include <cpu/x86/post_code.h>
-/***************************************************************************
-/**
-/**	DCacheSetup
-/**
-/**	Setup data cache for  use as RAM for a stack.
-/**
-/***************************************************************************/
-DCacheSetup:
-	/* Save the BIST result */
-	movl    %eax, %ebx
-
-	invd
-	/* set cache properties */
-	movl	$CPU_RCONF_DEFAULT, %ecx
-	rdmsr
-	movl	$0x010010000, %eax		/*1MB system memory in write back 1|00100|00 */
-	wrmsr
-
-	/* in LX DCDIS is set after POR which disables the cache..., clear this bit */
-	movl	CPU_DM_CONFIG0,%ecx
-	rdmsr
-	andl	$(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax	/* TODO: make consistent with i$ init,	either whole reg = 0,  or just this bit... */
-	wrmsr
-
-	/* get cache timing params from BIOS config data locations and apply */
-	/* fix delay controls for DM and IM arrays */
-	/* fix delay controls for DM and IM arrays */
-	movl	$CPU_BC_MSS_ARRAY_CTL0, %ecx
-	xorl	%edx, %edx
-	movl	$0x2814D352, %eax
-	wrmsr
-
-	movl	$CPU_BC_MSS_ARRAY_CTL1, %ecx
-	xorl	%edx, %edx
-	movl	$0x1068334D, %eax
-	wrmsr
-
-	movl	$CPU_BC_MSS_ARRAY_CTL2, %ecx
-	movl	$0x00000106, %edx
-	movl	$0x83104104, %eax
-	wrmsr
-
-	movl	$GLCP_FIFOCTL, %ecx
-	rdmsr
-	movl	$0x00000005, %edx
-	wrmsr
-
-	/* Enable setting */
-	movl	$CPU_BC_MSS_ARRAY_CTL_ENA, %ecx
-	xorl	%edx, %edx
-	movl	$0x01, %eax
-	wrmsr
-
-	/* Get cleaned up. */
-	xorl	%edi, %edi
-	xorl	%esi, %esi
-	xorl	%ebp, %ebp
-
-	/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */
-	/* remember,  there is NO stack yet... */
-
-	/* Tell cache we want to fill WAY 0 starting at the top */
-	xorl	%edx, %edx
-	xorl	%eax, %eax
-	movl	$CPU_DC_INDEX, %ecx
-	wrmsr
-
-	/* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */
-	movl	$LX_STACK_BASE, %ebp	/* init to start address */
-	orl		$1, %ebp				/* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */
-
-	/* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */
-	movl	$LX_NUM_CACHELINES, %edi
-DCacheSetupFillWay:
-
-	/* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */
-	/* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */
-	movw	$0x04, %si
-	xorl	%edx, %edx
-	xorl	%eax, %eax
-	movl	$CPU_DC_DATA, %ecx
-DCacheSetup_quadWordLoop:
-	wrmsr
-	decw	%si
-	jnz	DCacheSetup_quadWordLoop
-
-	/* Set the tag for this line,  need to do this for every new cache line to validate it! */
-	/* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */
-	xorl	%edx, %edx
-	movl	%ebp, %eax
-	movl	$CPU_DC_TAG, %ecx
-	wrmsr
-
-	/* switch to next line */
-	/* lines are in Bits10:4 */
-	/* when index is crossing 0x7F -> 0x80	writing a RSVD bit as 0x80 is not a valid CL anymore! */
-	movl	$CPU_DC_INDEX, %ecx
-	rdmsr
-	addl	$0x010, %eax /* TODO: prob. would be more elegant to calc. this from counter var edi... */
-	wrmsr
-
-	decl	%edi
-	jnz	DCacheSetupFillWay
-
-	/* 1 Way has been filled,  forward start address for next Way,	terminate if we have reached end of desired address range */
-	addl	$LX_CACHEWAY_SIZE, %ebp
-	cmpl	$LX_STACK_END, %ebp
-	jge	leave_DCacheSetup
-	movl	$LX_NUM_CACHELINES, %edi
-
-	/* switch to next way */
-	movl	$CPU_DC_INDEX, %ecx
-	rdmsr
-	addl	$0x01, %eax
-	andl	$0xFFFFF80F, %eax /* lets be sure: reset line index Bits10:4 */
-	wrmsr
-
-	jmp	DCacheSetupFillWay
-
-leave_DCacheSetup:
-	xorl	%edi, %edi
-	xorl	%esi, %esi
-	xorl	%ebp, %ebp
-
-	/* Disable the cache,  but ... DO NOT INVALIDATE the tags. */
-	/* Memory reads and writes will all hit in the cache. */
-	/* Cache updates and memory write-backs will not occur ! */
-	movl	%cr0, %eax
-	orl		$(CR0_CD + CR0_NW), %eax	/* set the CD and NW bits */
-	movl	%eax, %cr0
-
-	/* Now point sp to the cached stack. */
-	/* The stack will be fully functional at this location. No system memory is required at all ! */
-	/* set up the stack pointer */
-	movl	$LX_STACK_END, %eax
-	movl	%eax, %esp
-
-	/* test the stack*/
-	movl	$0x0F0F05A5A, %edx
-	pushl	%edx
-	popl	%ecx
-	cmpl	%ecx, %edx
-	je	DCacheSetupGood
-
-	post_code(0xc5)
-DCacheSetupBad:
-	hlt		/* issues */
-	jmp DCacheSetupBad
-DCacheSetupGood:
-	/* Go do early init and memory setup */
-
-	/* Restore the BIST result */
-	movl	%ebx, %eax
-	movl	%esp, %ebp
-	pushl	%eax
-
-	post_code(0x23)
-
-	/* Call romstage.c main function */
-	call	main
-done_cache_as_ram_main:
-
-        /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
-
-        push   %edi
-        mov    $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
-        push   %esi
-        mov    $(CONFIG_DCACHE_RAM_BASE),%edi
-        mov    %edi,%esi
-        cld
-        rep movsl %ds:(%esi),%es:(%edi)
-        pop    %esi
-        pop    %edi
-
-	/* Clear the cache out to ram */
-	wbinvd
-        /* re-enable the cache */
-        movl    %cr0, %eax
-        xorl             $(CR0_CD + CR0_NW), %eax        /* clear  the CD and NW bits */
-        movl    %eax, %cr0
-
-	/* clear boot_complete flag */
-	xorl	%ebp, %ebp
-__main:
-	post_code(POST_PREPARE_RAMSTAGE)
-
-	/* TODO For suspend/resume the cache will have to live between
-	 * CONFIG_RAMBASE and CONFIG_RAMTOP
-	 */
-
-	cld				/* clear direction flag */
-
-	/* copy coreboot from it's initial load location to
-	 * the location it is compiled to run at.
-	 * Normally this is copying from FLASH ROM to RAM.
-	 */
-	movl	%ebp, %esi
-	pushl	%esi
-	call copy_and_run
-
-.Lhlt:
-	post_code(POST_DEAD_CODE)
-	hlt
-	jmp	.Lhlt
-
diff --git a/src/cpu/amd/model_lx/cpubug.c b/src/cpu/amd/model_lx/cpubug.c
deleted file mode 100644
index e3b6e511ee..0000000000
--- a/src/cpu/amd/model_lx/cpubug.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <stdlib.h>
-#include <string.h>
-#include <bitops.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-
-/**************************************************************************
- *
- *	pcideadlock
- *
- *	Bugtool #465 and #609
- *	PCI cache deadlock
- *	There is also fix code in cache and PCI functions. This bug is very is pervasive.
- *
- **************************************************************************/
-static void pcideadlock(void)
-{
-	msr_t msr;
-
-	/*
-	 * forces serialization of all load misses. Setting this bit prevents the
-	 * DM pipe from backing up if a read request has to be held up waiting
-	 * for PCI writes to complete.
-	 */
-	msr = rdmsr(CPU_DM_CONFIG0);
-	msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
-	wrmsr(CPU_DM_CONFIG0, msr);
-
-	/* write serialize memory hole to PCI. Need to unWS when something is
-	 * shadowed regardless of cachablility.
-	 */
-	msr.lo = 0x021212121;
-	msr.hi = 0x021212121;
-	wrmsr(CPU_RCONF_A0_BF, msr);
-	wrmsr(CPU_RCONF_C0_DF, msr);
-	wrmsr(CPU_RCONF_E0_FF, msr);
-}
-
-/****************************************************************************/
-/***/
-/**	DisableMemoryReorder*/
-/***/
-/**	PBZ 3659:*/
-/**	 The MC reordered transactions incorrectly and breaks coherency.*/
-/**	 Disable reording and take a potential performance hit.*/
-/**	 This is safe to do here and not in MC init since there is nothing*/
-/**	 to maintain coherency with and the cache is not enabled yet.*/
-/***/
-/****************************************************************************/
-static void disablememoryreadorder(void)
-{
-	msr_t msr;
-
-	msr = rdmsr(MC_CF8F_DATA);
-	msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
-	wrmsr(MC_CF8F_DATA, msr);
-}
-
-/* For cpu version C3. Should be the only released version */
-void cpubug(void)
-{
-	pcideadlock();
-	disablememoryreadorder();
-	printk(BIOS_DEBUG, "Done cpubug fixes \n");
-}
diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c
deleted file mode 100644
index bad98b51bf..0000000000
--- a/src/cpu/amd/model_lx/cpureginit.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/**************************************************************************
-;*
-;*	SetDelayControl
-;*
-;*************************************************************************/
-#include "cpu/x86/msr.h"
-
-
-
-
-/**
- * Delay Control Settings table from AMD (MCP 0x4C00000F).
- */
-static const msrinit_t delay_msr_table[] = {
-	{CPU_BC_MSS_ARRAY_CTL0, {.hi = 0x00000000, .lo = 0x2814D352}},
-	{CPU_BC_MSS_ARRAY_CTL1, {.hi = 0x00000000, .lo = 0x1068334D}},
-	{CPU_BC_MSS_ARRAY_CTL2, {.hi = 0x00000106, .lo = 0x83104104}},
-};
-
-
-
-static const struct delay_controls {
-	u8 dimms;
-	u8 devices;
-	u32 slow_hi;
-	u32 slow_low;
-	u32 fast_hi;
-	u32 fast_low;
-} delay_control_table[] = {
-	/* DIMMs Devs Slow (<=333MHz)            Fast (>334MHz) */
-	{   1,     4, 0x0837100FF, 0x056960004,  0x0827100FF, 0x056960004 },
-	{   1,     8, 0x0837100AA, 0x056960004,  0x0827100AA, 0x056960004 },
-	{   1,    16, 0x0837100AA, 0x056960004,  0x082710055, 0x056960004 },
-	{   2,     8, 0x0837100A5, 0x056960004,  0x082710000, 0x056960004 },
-	{   2,    16, 0x0937100A5, 0x056960004,  0x0C27100A5, 0x056960004 },
-	{   2,    20, 0x0B37100A5, 0x056960004,  0x0B27100A5, 0x056960004 },
-	{   2,    24, 0x0B37100A5, 0x056960004,  0x0B27100A5, 0x056960004 },
-	{   2,    32, 0x0B37100A5, 0x056960004,  0x0B2710000, 0x056960004 },
-};
-
-/*
- * Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM
- * in slot 0, but it should be clear for all 2 DIMM settings and if a
- * single DIMM is in slot 1. Bits 54:52 should always be set to '111'.
- *
- * Settings for single DIMM and no VTT termination (like DB800 platform)
- * 0xF2F100FF 0x56960004
- * -------------------------------------
- * ADDR/CTL have 22 ohm series R
- * DQ/DQM/DQS have 33 ohm series R
- */
-
-/**
- * This is Black Magic DRAM timing juju[1].
- *
- * DRAM delay depends on CPU clock, memory bus clock, memory bus loading,
- * memory bus termination, your middle initial (ha! caught you!), GeodeLink
- * clock rate, and DRAM timing specifications.
- *
- * From this the code computes a number which is "known to work". No,
- * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger)
- * is hooked up, then just don't do anything. This code was written by a master
- * of the Dark Arts at AMD and should not be modified in any way.
- *
- * [1] (http://www.thefreedictionary.com/juju)
- *
- * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent).
- * @param dimm1 The SMBus address of DIMM 1 (mainboard dependent).
- * @param terminated The bus is terminated. (mainboard dependent).
- */
-static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated)
-{
-	u32 glspeed;
-	u8 spdbyte0, spdbyte1, dimms, i;
-	msr_t msr;
-
-	glspeed = GeodeLinkSpeed();
-
-	/* Fix delay controls for DM and IM arrays. */
-	for (i = 0; i < ARRAY_SIZE(delay_msr_table); i++)
-		wrmsr(delay_msr_table[i].index, delay_msr_table[i].msr);
-
-	msr = rdmsr(GLCP_FIFOCTL);
-	msr.hi = 0x00000005;
-	wrmsr(GLCP_FIFOCTL, msr);
-
-	/* Enable setting. */
-	msr.hi = 0;
-	msr.lo = 0x00000001;
-	wrmsr(CPU_BC_MSS_ARRAY_CTL_ENA, msr);
-
-	/* Debug Delay Control setup check.
-	 * Leave it alone if it has been setup. FS2 or something is here.
-	 */
-	msr = rdmsr(GLCP_DELAY_CONTROLS);
-	if (msr.lo & ~(DELAY_LOWER_STATUS_MASK))
-		return;
-
-	/* Delay Controls based on DIMM loading. UGH!
-	 * Number of devices = module width (SPD 6) / device width (SPD 13)
-	 *                     * physical banks (SPD 5)
-	 *
-	 * Note: We only support a module width of 64.
-	 */
-	dimms = 0;
-	spdbyte0 = spd_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH);
-	if (spdbyte0 != 0xFF) {
-		dimms++;
-		spdbyte0 = (u8)64 / spdbyte0 *
-			   (u8)(spd_read_byte(dimm0, SPD_NUM_DIMM_BANKS));
-	} else {
-		spdbyte0 = 0;
-	}
-
-	spdbyte1 = spd_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH);
-	if (spdbyte1 != 0xFF) {
-		dimms++;
-		spdbyte1 = (u8)64 / spdbyte1 *
-			   (u8)(spd_read_byte(dimm1, SPD_NUM_DIMM_BANKS));
-	} else {
-		spdbyte1 = 0;
-	}
-
-	/* Zero GLCP_DELAY_CONTROLS MSR */
-	msr.hi = msr.lo = 0;
-
-	/* Save some power, disable clock to second DIMM if it is empty. */
-	if (spdbyte1 == 0)
-		msr.hi |= DELAY_UPPER_DISABLE_CLK135;
-
-	spdbyte0 += spdbyte1;
-
-	if ((dimms == 1) && (terminated == DRAM_TERMINATED)) {
-		msr.hi = 0xF2F100FF;
-		msr.lo = 0x56960004;
-	} else for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) {
-		if ((dimms == delay_control_table[i].dimms) &&
-		    (spdbyte0 <= delay_control_table[i].devices)) {
-			if (glspeed < 334) {
-				msr.hi |= delay_control_table[i].slow_hi;
-				msr.lo |= delay_control_table[i].slow_low;
-			} else {
-				msr.hi |= delay_control_table[i].fast_hi;
-				msr.lo |= delay_control_table[i].fast_low;
-			}
-			break;
-		}
-	}
-	wrmsr(GLCP_DELAY_CONTROLS, msr);
-}
-
-/* ***************************************************************************/
-/* *	cpuRegInit*/
-/* ***************************************************************************/
-void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
-{
-	int msrnum;
-	msr_t msr;
-
-	/* Castle 2.0 BTM periodic sync period. */
-	/*      [40:37] 1 sync record per 256 bytes */
-	print_debug("Castle 2.0 BTM periodic sync period.\n");
-	msrnum = CPU_PF_CONF;
-	msr = rdmsr(msrnum);
-	msr.hi |= (0x8 << 5);
-	wrmsr(msrnum, msr);
-
-	/*
-	 * LX performance setting.
-	 * Enable Quack for fewer re-RAS on the MC
-	 */
-	print_debug("Enable Quack for fewer re-RAS on the MC\n");
-	msrnum = GLIU0_ARB;
-	msr = rdmsr(msrnum);
-	msr.hi &= ~ARB_UPPER_DACK_EN_SET;
-	msr.hi |= ARB_UPPER_QUACK_EN_SET;
-	wrmsr(msrnum, msr);
-
-	msrnum = GLIU1_ARB;
-	msr = rdmsr(msrnum);
-	msr.hi &= ~ARB_UPPER_DACK_EN_SET;
-	msr.hi |= ARB_UPPER_QUACK_EN_SET;
-	wrmsr(msrnum, msr);
-
-	/* GLIU port active enable, limit south pole masters
-	 * (AES and PCI) to one outstanding transaction.
-	 */
-	print_debug(" GLIU port active enable\n");
-	msrnum = GLIU1_PORT_ACTIVE;
-	msr = rdmsr(msrnum);
-	msr.lo &= ~0x880;
-	wrmsr(msrnum, msr);
-
-	/* Set the Delay Control in GLCP */
-	print_debug("Set the Delay Control in GLCP\n");
-	SetDelayControl(dimm0, dimm1, terminated);
-
-	/*  Enable RSDC */
-	print_debug("Enable RSDC\n");
-	msrnum = CPU_AC_SMM_CTL;
-	msr = rdmsr(msrnum);
-	msr.lo |= SMM_INST_EN_SET;
-	wrmsr(msrnum, msr);
-
-	/* FPU imprecise exceptions bit */
-	print_debug("FPU imprecise exceptions bit\n");
-	msrnum = CPU_FPU_MSR_MODE;
-	msr = rdmsr(msrnum);
-	msr.lo |= FPU_IE_SET;
-	wrmsr(msrnum, msr);
-
-	/* Power Savers (Do after BIST) */
-	/* Enable Suspend on HLT & PAUSE instructions */
-	print_debug("Enable Suspend on HLT & PAUSE instructions\n");
-	msrnum = CPU_XC_CONFIG;
-	msr = rdmsr(msrnum);
-	msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
-	wrmsr(msrnum, msr);
-
-	/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
-	print_debug("Enable SUSP and allow TSC to run in Suspend\n");
-	msrnum = CPU_BC_CONF_0;
-	msr = rdmsr(msrnum);
-	msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
-	msr.lo &= 0x0F0FFFFFF;
-	msr.lo |= 0x002000000;	/* PBZ213: Set PAUSEDLY = 2 */
-	wrmsr(msrnum, msr);
-
-	/* Disable the debug clock to save power. */
-	/* NOTE: leave it enabled for fs2 debug */
-	if (debug_clock_disable && 0) {
-		msrnum = GLCP_DBGCLKCTL;
-		msr.hi = 0;
-		msr.lo = 0;
-		wrmsr(msrnum, msr);
-	}
-
-	/* Setup throttling delays to proper mode if it is ever enabled. */
-	print_debug("Setup throttling delays to proper mode\n");
-	msrnum = GLCP_TH_OD;
-	msr.hi = 0;
-	msr.lo = 0x00000603C;
-	wrmsr(msrnum, msr);
-	print_debug("Done cpuRegInit\n");
-}
diff --git a/src/cpu/amd/model_lx/model_lx_init.c b/src/cpu/amd/model_lx/model_lx_init.c
deleted file mode 100644
index 85e6bfbb27..0000000000
--- a/src/cpu/amd/model_lx/model_lx_init.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
- * Copyright (C) 2006 Stefan Reinauer <stepan@coresystems.de>
- * Copyright (C) 2006 Andrei Birjukov <andrei.birjukov@artecdesign.ee>
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/cache.h>
-#include <arch/io.h>
-
-static void vsm_end_post_smi(void)
-{
-	__asm__ volatile ("push %ax\n"
-			  "mov $0x5000, %ax\n"
-			  ".byte 0x0f, 0x38\n" "pop %ax\n");
-}
-
-static void model_lx_init(device_t dev)
-{
-	printk(BIOS_DEBUG, "model_lx_init\n");
-
-	/* Turn on caching if we haven't already */
-	x86_enable_cache();
-
-	/* Enable the local cpu apics */
-	//setup_lapic();
-
-	// do VSA late init
-	vsm_end_post_smi();
-
-	// Set gate A20 (legacy vsm disables it in late init)
-	printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));
-	outb(0x02, 0x92);
-	printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));
-
-	printk(BIOS_DEBUG, "CPU model_lx_init DONE\n");
-};
-
-static struct device_operations cpu_dev_ops = {
-	.init = model_lx_init,
-};
-
-static struct cpu_device_id cpu_table[] = {
-	{X86_VENDOR_AMD, 0x05A2},
-	{0, 0},
-};
-
-static const struct cpu_driver driver __cpu_driver = {
-	.ops = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c
deleted file mode 100644
index 11182501c1..0000000000
--- a/src/cpu/amd/model_lx/msrinit.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdlib.h>
-#include "cpu/x86/msr.h"
-
-static const msrinit_t msr_table[] =
-{
-	{CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB.
-								   * Rom Properties: Write Serialize, WriteProtect.
-								   * RomBase: 0xFFFC0
-								   * SysTop to RomBase Properties: Write Back.
-								   * SysTop: 0x000A0
-								   * System Memory Properties:  (Write Back) */
-	{CPU_RCONF_A0_BF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
-	{CPU_RCONF_C0_DF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
-	{CPU_RCONF_E0_FF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
-
-	/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
-	{MSR_GLIU0_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
-	{MSR_GLIU0_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
-	{MSR_GLIU0_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-	{MSR_GLIU1_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
-	{MSR_GLIU1_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
-	{MSR_GLIU1_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-
-	/* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory.
-	 * It doesn't really matter in fact how much, however, because the only usage
-	 * of this extended memory will be to host the coreboot_ram stage at RAMBASE,
-	 * currently 1Mb.
-	 * These registers will be set to their correct value by the Northbridge init code.
-	 *
-	 * WARNING: if coreboot_ram could not be loaded, these registers are probably
-	 * incorrectly set here. You may comment the following two lines and set RAMBASE
-	 * to 0x4000 to revert to the previous behavior for LX-boards.
-	 */
-	{MSR_GLIU0_SYSMEM,  {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
-	{MSR_GLIU1_SYSMEM,  {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
-};
-
-static void msr_init(void)
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(msr_table); i++)
-		wrmsr(msr_table[i].index, msr_table[i].msr);
-}
-
-
diff --git a/src/cpu/amd/model_lx/syspreinit.c b/src/cpu/amd/model_lx/syspreinit.c
deleted file mode 100644
index 35c54fba5f..0000000000
--- a/src/cpu/amd/model_lx/syspreinit.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/* ***************************************************************************/
-/* **/
-/* *	StartTimer1*/
-/* **/
-/* *	Entry: none*/
-/* *	Exit: Starts Timer 1 for port 61 use*/
-/* *	Destroys: Al,*/
-/* **/
-/* ***************************************************************************/
-static void StartTimer1(void)
-{
-	outb(0x56, 0x43);
-	outb(0x12, 0x41);
-}
-
-void SystemPreInit(void)
-{
-
-	/* they want a jump ... */
-#if !CONFIG_CACHE_AS_RAM
-	__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
-#endif
-	StartTimer1();
-}