Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-27

Creator:  Hamish Guthrie <hamish@prodigi.ch>

Added GX1 cpu files


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 121 insertions, 0 deletions

diff --git a/src/cpu/amd/model_gx1/Config.lb b/src/cpu/amd/model_gx1/Config.lb
new file mode 100644
index 0000000000..bf76bd97f0
--- /dev/null
+++ b/src/cpu/amd/model_gx1/Config.lb
@@ -0,0 +1,6 @@
+dir /cpu/x86/tsc
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+driver model_gx1_init.o
diff --git a/src/cpu/amd/model_gx1/cpu_setup.inc b/src/cpu/amd/model_gx1/cpu_setup.inc
new file mode 100644
index 0000000000..adb8cdc267
--- /dev/null
+++ b/src/cpu/amd/model_gx1/cpu_setup.inc
@@ -0,0 +1,68 @@
+/*
+    freebios/src/northbridge/nsc/gx1/cpu_setup.inc
+
+    Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
+
+    Initialize the GX1 CPU configuration registers
+*/
+
+/* USES: esi, ecx, eax */
+
+#include "gx1def.h"
+
+	movl %eax, %ebp /* preserve bist */
+
+cpu_setup_start:
+	leal	cpu_setup_table, %esi
+	movl	$cpu_setup_len, %ecx
+
+cpu_setup_loop:
+	movw	(%esi), %ax
+	addl	$2, %esi
+	outb	%al, $0x22
+	movb	%ah, %al
+	outb	%al, $0x23
+	loop	cpu_setup_loop
+
+	movb	$0xff, %al		/* DIR1 -- Identification Register 1 */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	cmpb	$0x63, %al		/* Revision for GXLV rev 3 */
+	jbe	cpu_no_ccr4
+
+	movb	$0xe8, %al		/* CCR4 */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	orb	$0x20, %al		/* Enable FPU Fast Mode */
+	outb	%al, $0x23
+
+	movb	$0xf0, %al		/* PCR1 --- Performace Control  */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	orb	$0x02, %al		/* Incrementor on, whatever that is */
+	outb	%al, $0x23
+
+	movb	$0x20, %al		/* PCR0 --- Performace Control  */
+	outb	%al, $0x22
+	inb	$0x23, %al
+	orb	$0x20, %al		/* Must be 1 according to data book */
+	orb	$0x04, %al		/* Incrementor Margin 10 */
+	outb	%al, $0x23
+cpu_no_ccr4:
+
+	jmp	cpu_setup_end
+
+cpu_setup_table:
+	.byte	0xc1, 0x00		/* NO SMIs */
+	.byte	0xc3, 0x14		/* Enable CPU config register */
+	.byte	0x20, 0x00
+	.byte	0xb8, GX_BASE>>30	/* Enable GXBASE address */
+	.byte	0xc2, 0x00
+	.byte	0xe8, 0x98
+	.byte	0xc3, 0xf8		/* Enable CPU config register */
+cpu_setup_len = (.-cpu_setup_table)/2
+
+cpu_setup_end:
+	nop
+
+	movl %ebp, %eax	/* Restore bist */
diff --git a/src/cpu/amd/model_gx1/gx_setup.inc b/src/cpu/amd/model_gx1/gx_setup.inc
new file mode 100644
index 0000000000..60c2bb02d0
--- /dev/null
+++ b/src/cpu/amd/model_gx1/gx_setup.inc
@@ -0,0 +1,47 @@
+/*
+    freebios/src/northbridge/nsc/gx1/gx_setup.inc
+
+    Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
+
+    Setup the GX_BASE registers on a National Semiconductor Geode CPU
+*/
+
+#include "gx1def.h"
+
+	movl %eax, %ebp /* Preserve bist */
+
+gx_setup_start:
+	leal	gx_setup_table, %esi
+	movl	$gx_setup_len, %ecx
+	movl	$GX_BASE, %edi
+
+gx_setup_loop:
+	movw	(%esi), %di		/* Only read the low word of address */
+	addl	$4, %esi
+	movl	(%esi), %eax		/* Data */
+	addl	$4, %esi
+	movl	%eax, (%edi)
+	loop	gx_setup_loop
+
+	jmp	gx_setup_end
+
+gx_setup_table:
+	/* Allow writes to config registers */
+	.long	DC_UNLOCK, DC_UNLOCK_MAGIC
+	.long	DC_GENERAL_CFG, 0
+	.long	DC_UNLOCK, 0
+
+	.long	BC_DRAM_TOP, 0x3fffffff
+	.long	BC_XMAP_1, 0x60
+	.long	BC_XMAP_2, 0
+	.long	BC_XMAP_3, 0
+
+	.long	MC_BANK_CFG, 0x00700070	/* No DIMMS installed */
+	.long	MC_MEM_CNTRL1, XBUSARB
+	.long	MC_GBASE_ADD, 0x7ff	/* Almost 1GB */
+gx_setup_len = (.-gx_setup_table)/8
+
+gx_setup_end:
+	nop
+
+	movl %ebp, %eax	/* Restore bist */