core range and set_init_ram_access

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 23 insertions, 11 deletions

diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index e60aa35bf9..50b1532f26 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -10,7 +10,10 @@
 
 typedef void (*process_ap_t)(unsigned apicid, void *gp);
 
-static void for_each_ap(unsigned bsp_apicid, unsigned core0_only, process_ap_t process_ap, void *gp)
+//core_range = 0 : all cores
+//core range = 1 : core 0 only
+//core range = 2 : cores other than core0
+static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t process_ap, void *gp)
 {
 	// here assume the OS don't change our apicid
 	unsigned ap_apicid;
@@ -49,16 +52,20 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core0_only, process_ap_t p
                 }
                 siblings = j;
 
-		unsigned jj;
+                unsigned jstart, jend;
+
+                if(core_range == 2) {
+                        jstart = 1;
+                }
+
+                if(e0_later_single_core || disable_siblings || (core_range==1)) {
+                        jend = 0;
+                } else {
+                        jend = siblings;
+                }
 
-		if(e0_later_single_core || disable_siblings || core0_only) {
-			jj = 0;
-		} else {
-			jj = siblings;
-		}	
-		
-	
-                for(j=0; j<=jj; j++) {
+
+                for(j=jstart; j<=jend; j++) {
 
                         ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
 
@@ -145,6 +152,11 @@ static void wait_all_aps_started(unsigned bsp_apicid)
         for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0);
 }
 
+static void wait_all_other_cores_started(unsigned bsp_apicid)
+{
+        for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0);
+}
+
 static void allow_all_aps_stop(unsigned bsp_apicid)
 {
         lapic_write(LAPIC_MSG_REG, (bsp_apicid<<24) | 0x44); // allow aps to stop
@@ -243,7 +255,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
 			wait_cpu_state(bsp_apicid, 0x44);
 			lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
 
-			set_init_ram_access(); //inline
+			set_init_ram_access();
 			disable_cache_as_ram(); // inline
                         stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... 
                 }