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authorMyles Watson <mylesgw@gmail.com>2009-10-16 16:32:57 +0000
committerMyles Watson <mylesgw@gmail.com>2009-10-16 16:32:57 +0000
commit0f61a4fc98f135c0ed22c67ee3241bf5670a61e2 (patch)
treeb3867408477cdf8a3a2374f32d91b4f3936b7486 /src/cpu/amd/model_fxx
parent9969bdc4fb3d36a39ed9efb67ef0bf638a4e8e09 (diff)
Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP to match CONFIG_RAMBASE.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_fxx')
-rw-r--r--src/cpu/amd/model_fxx/model_fxx_init.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index d183bf89bc..8b68098019 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -33,7 +33,7 @@
void cpus_ready_for_init(void)
{
#if CONFIG_MEM_TRAIN_SEQ == 1
- struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained
wait_all_core0_mem_trained(sysinfox);
#endif
@@ -182,7 +182,7 @@ static void set_init_ecc_mtrrs(void)
msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
wrmsr(MTRRphysBase_MSR(0), msr);
msr.hi = 0x000000ff;
- msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800;
+ msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800;
wrmsr(MTRRphysMask_MSR(0), msr);
/* Set the default type to write combining */
@@ -308,8 +308,8 @@ static void init_ecc_memory(unsigned node_id)
/* Don't start too early */
begink = startk;
- if (begink < CONFIG_LB_MEM_TOPK) {
- begink = CONFIG_LB_MEM_TOPK;
+ if (begink < (CONFIG_RAMTOP >> 10)) {
+ begink = (CONFIG_RAMTOP >>10);
}
printk_debug("Clearing memory %luK - %luK: ", begink, endk);