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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-02 20:25:03 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-07 01:41:59 +0200 |
| commit | fb39f82116f0411ee85e3d91bfd97237c34debbb (patch) | |
| tree | 5a3f3ce0fff3b021f081aa8e5a29acc5f9c21b91 /src/cpu/amd/model_10xxx | |
| parent | a97e0075a22af82ede8ab70a7e26d2a9e88490ea (diff) | |
cpu/amd/car: Move AP stacks below the BSP stack to free up space
Caching SPD data during startup requires additional CAR space.
There was a large chunk of free space between the AP stack top and
the BSP stack bottom; moving the AP stacks below the BSP stack
allows this space to be utilized.
TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores)
and 120k of CAR.
Change-Id: I370ff368affde7061d6547527bda058b9016e977
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10404
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/cpu/amd/model_10xxx')
| -rw-r--r-- | src/cpu/amd/model_10xxx/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 5 |
2 files changed, 8 insertions, 1 deletions
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 4b5cdedaa1..ebd282a5ca 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -34,6 +34,10 @@ config DCACHE_BSP_STACK_SIZE hex default 0x2000 +config DCACHE_BSP_STACK_SLUSH + hex + default 0x1000 + config DCACHE_AP_STACK_SIZE hex default 0x400 diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 7e79307c89..4c72848986 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -250,8 +250,11 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) u32 apicid; struct node_core_id id; + /* Please refer to the calculations and explaination in cache_as_ram.inc before modifying these values */ uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE; - uint32_t bsp_stack_region_lower_boundary = CONFIG_DCACHE_RAM_BASE + (CONFIG_DCACHE_RAM_SIZE / 2); + uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH; + uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE; + uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size; void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); if (((void*)(sysinfo + 1)) > lower_stack_region_boundary) printk(BIOS_WARNING, |