diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-06 21:50:21 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-06 21:50:21 +0000 |
commit | 8f2c616dbc7f36bf63d61960c2e14c6ca1c5af22 (patch) | |
tree | b1ede5972569c6aeb57961a5fdbd219019902c8f /src/cpu/amd/model_10xxx | |
parent | 233f186e95cf76d3a5bb5a7224769f63c36c5931 (diff) |
No warnings day, next round.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/model_10xxx')
-rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 0061706e3f..e701b4e8db 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -91,7 +91,7 @@ static void set_pci_mmio_conf_reg(void) wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg //mtrr for that range? -// set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE); + // set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE); set_wrap32dis(); @@ -293,7 +293,7 @@ static void enable_apic_ext_id(u32 node) } -static void STOP_CAR_AND_CPU() +static void STOP_CAR_AND_CPU(void) { msr_t msr; @@ -529,7 +529,7 @@ static void setup_remote_node(u8 node) } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ -void AMD_Errata281(u8 node, u32 revision, u32 platform) +static void AMD_Errata281(u8 node, u32 revision, u32 platform) { /* Workaround for Transaction Scheduling Conflict in * Northbridge Cross Bar. Implement XCS Token adjustment @@ -591,7 +591,7 @@ void AMD_Errata281(u8 node, u32 revision, u32 platform) } -void AMD_Errata298(void) +static void AMD_Errata298(void) { /* Workaround for L2 Eviction May Occur during operation to * set Accessed or dirty bit. |