summaryrefslogtreecommitdiff
path: root/src/cpu/amd/microcode
diff options
context:
space:
mode:
authorli feng <li1.feng@intel.com>2018-05-22 12:49:53 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-07-09 09:24:42 +0000
commit2106638ec2d7869f396310882bf5e9fa52dbf3c0 (patch)
treea97b2e28bca8c5625b92647dd6f5b23ec29bf4a8 /src/cpu/amd/microcode
parentf1114d891865e70ae1f2ba58844fec11d055ae3a (diff)
soc/intel/skylake: config ISH in SOC side
Config ISH in SOC side by checking if ISH device is turned on. "IshEnable" is not needed anymore since ISH device on/off will tell if ISH should be enabled or not. "IshEnable" will be removed from chip.h in separate CL. Atlas board specific ISH setting is needed, which is committed in separate CL. BUG=b:79244403 BRANCH=none TEST=Verified on Atlas board with ISH rework. ISH log showed on console. Change-Id: I3fc8648b3e6551497617ef1ebd2889245cdd31c3 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/cpu/amd/microcode')
0 files changed, 0 insertions, 0 deletions