diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2013-07-08 16:23:54 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-11 22:36:59 +0200 |
| commit | 4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c (patch) | |
| tree | 6bd8440a05f6ea1184c0a5500d43cc92ab683f01 /src/cpu/amd/geode_gx2 | |
| parent | 0cb07e3476d9408d0935253f9f26c0a8ddc28401 (diff) | |
cpu: Fix spelling
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/geode_gx2')
| -rw-r--r-- | src/cpu/amd/geode_gx2/cpubug.c | 6 | ||||
| -rw-r--r-- | src/cpu/amd/geode_gx2/cpureginit.c | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c index 54d7e0e8d2..eddc92408e 100644 --- a/src/cpu/amd/geode_gx2/cpubug.c +++ b/src/cpu/amd/geode_gx2/cpubug.c @@ -163,7 +163,7 @@ static void eng2900(void) * clocks when CPU is snooped. Because setting XSTATE to 0 * overrides any other XSTATE action, the code will always * stall for 4 GeodeLink clocks after a snoop request goes - * away even if it occured a clock or two later than a + * away even if it occurred a clock or two later than a * different snoop; the stall signal will never 'glitch high' * for only one or two CPU clocks with this code. */ @@ -201,7 +201,7 @@ static void eng2900(void) msr.lo = 0x30000; wrmsr(MSR_GLCP + 0x0073, msr); - /* Writing action number 5: STALL_CPU_PIPE when exitting idle + /* Writing action number 5: STALL_CPU_PIPE when exiting idle state or not in idle state */ msr.hi = 0; msr.lo = 0x00430000; @@ -293,7 +293,7 @@ static void bug118339(void) * * PBZ 3659: * The MC reordered transactions incorrectly and breaks coherency. - * Disable reording and take a potential performance hit. + * Disable reordering and take a potential performance hit. * This is safe to do here and not in MC init since there is nothing * to maintain coherency with and the cache is not enabled yet. */ diff --git a/src/cpu/amd/geode_gx2/cpureginit.c b/src/cpu/amd/geode_gx2/cpureginit.c index 0fc852d531..e0ecd62722 100644 --- a/src/cpu/amd/geode_gx2/cpureginit.c +++ b/src/cpu/amd/geode_gx2/cpureginit.c @@ -15,7 +15,7 @@ void cpuRegInit (void) /* Set up GLCP to grab BTM data. */ msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */ msr.hi = 0x0; - msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out, */ + msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */ wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */ /* Turn off debug clock */ @@ -119,7 +119,7 @@ void cpuRegInit (void) wrmsr(msrnum, msr); } -/* FPU impercise exceptions bit */ +/* FPU imprecise exceptions bit */ { msrnum = CPU_FPU_MSR_MODE; msr = rdmsr(msrnum); |