diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/cpu/amd/family_10h-family_15h/monotonic_timer.c | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/cpu/amd/family_10h-family_15h/monotonic_timer.c')
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/monotonic_timer.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c index 6bf046dedc..b1886eaca3 100644 --- a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c +++ b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c @@ -16,12 +16,11 @@ #include <stdint.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <timer.h> #include <device/pci.h> #include <device/pci_ids.h> - #include <northbridge/amd/amdht/AsPsDefs.h> -#include <cpu/amd/msr.h> static struct monotonic_counter { int initialized; @@ -62,7 +61,7 @@ static void init_timer(void) wrmsr(HWCR_MSR, msr); /* Get core Pstate 0 frequency in MHz */ - msr = rdmsr(0xC0010064 + boost_capable); + msr = rdmsr(PSTATE_0_MSR + boost_capable); cpufid = (msr.lo & 0x3f); cpudid = (msr.lo & 0x1c0) >> 6; mono_counter.core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid); |