diff options
| author | Damien Zammit <damien@zamaudio.com> | 2016-11-28 00:29:10 +1100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-04 18:56:01 +0100 |
| commit | 75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7 (patch) | |
| tree | 618c2bc04f44cf73d3dae288bff0a5e2ef44d616 /src/cpu/amd/family_10h-family_15h/fidvid.c | |
| parent | 6c20b65849aeda664cc40ebc0f0bab2e99768423 (diff) | |
amdfam10: Perform major include ".c" cleanup
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Diffstat (limited to 'src/cpu/amd/family_10h-family_15h/fidvid.c')
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/fidvid.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 0e51a0c597..8fe708cbd7 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -89,8 +89,7 @@ b.- prep_fid_change(...) */ -#if CONFIG_SET_FIDVID - +#include <inttypes.h> #include <northbridge/amd/amdht/AsPsDefs.h> static inline void print_debug_fv(const char *str, u32 val) @@ -601,7 +600,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev, } } -static void prep_fid_change(void) +void prep_fid_change(void) { u32 dword; u32 nodes; @@ -981,7 +980,7 @@ static void finalPstateChange(void) set_pstate(0); } -static void init_fidvid_stage2(u32 apicid, u32 nodeid) +void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; pci_devfn_t dev; @@ -1052,7 +1051,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp) #endif -static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) +int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) { #if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st ap_apicidx; @@ -1098,4 +1097,3 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) return 0; // No FID/VID changes. Don't reset } -#endif |