diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2017-06-27 22:54:42 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-06-28 00:23:32 +0000 |
| commit | 168ef399c43ad79a40a8bbb2de921a2bd906b3f5 (patch) | |
| tree | 16613245bebd7920cf3e7ce41f0d7bb5441f05e2 /src/cpu/amd/dualcore | |
| parent | 70083a1de9e12d8dbd3ba70e7a36a7282090f0e0 (diff) | |
cpu/*: Add whitespace around '<<'
Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/dualcore')
| -rw-r--r-- | src/cpu/amd/dualcore/amd_sibling.c | 4 | ||||
| -rw-r--r-- | src/cpu/amd/dualcore/dualcore.c | 4 | ||||
| -rw-r--r-- | src/cpu/amd/dualcore/dualcore_id.c | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index 1c003c8319..693ceb87cd 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -59,7 +59,7 @@ static void enable_apic_ext_id(int nodes) uint32_t val; dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); val = pci_read_config32(dev, 0x68); - val |= (1<<17)|(1<<18); + val |= (1 << 17)|(1 << 18); pci_write_config32(dev, 0x68, val); } } @@ -84,7 +84,7 @@ unsigned get_apicid_base(unsigned ioapic_num) if (bsp_apic_id > 0) { // IOAPIC could start from 0 return 0; - } else if (pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0 + } else if (pci_read_config32(dev, 0x68) & ( (1 << 17) | (1 << 18)) ) { // enabled ext id but bsp = 0 return 1; } diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 83302ca9fe..1f25668c54 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -48,11 +48,11 @@ static inline void real_start_other_core(unsigned nodeid) uint32_t dword; // set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44); - dword |= 1<<27; // NbMcaToMstCpuEn bit + dword |= 1 << 27; // NbMcaToMstCpuEn bit pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword); // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68); - dword |= 1<<5; + dword |= 1 << 5; pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword); } diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index 80ce1c7c73..e7af552dcb 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -43,14 +43,14 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54) // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24] id.coreid = (cpuid_ebx(1) >> 24) & 0xf; id.nodeid = (id.coreid>>CORE_ID_BIT); - id.coreid &= ((1<<CORE_ID_BIT)-1); + id.coreid &= ((1 << CORE_ID_BIT)-1); } else { // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27] id.nodeid = (cpuid_ebx(1) >> 24) & 0xf; id.coreid = (id.nodeid>>NODE_ID_BIT); - id.nodeid &= ((1<<NODE_ID_BIT)-1); + id.nodeid &= ((1 << NODE_ID_BIT)-1); } return id; } |