src/cpu: Improve code formatting

Change-Id: I17d5efe382da5301a9f5d595186d0fb7576725ca
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16391
Tested-by: build bot (Jenkins)
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-by: Antonello Dettori <dev@dettori.io>

3 files changed, 37 insertions, 37 deletions

diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index 20f22fc49e..1c003c8319 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -51,17 +51,17 @@ static int get_max_siblings(int nodes)
 
 static void enable_apic_ext_id(int nodes)
 {
-        device_t dev;
-        int nodeid;
-
-        //enable APIC_EXIT_ID all the nodes
-        for (nodeid=0; nodeid<nodes; nodeid++){
-                uint32_t val;
-                dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
-                val = pci_read_config32(dev, 0x68);
+	device_t dev;
+	int nodeid;
+
+	//enable APIC_EXIT_ID all the nodes
+	for (nodeid=0; nodeid<nodes; nodeid++){
+		uint32_t val;
+		dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
+		val = pci_read_config32(dev, 0x68);
 		val |= (1<<17)|(1<<18);
 		pci_write_config32(dev, 0x68, val);
-        }
+	}
 }
 
 
@@ -72,13 +72,13 @@ unsigned get_apicid_base(unsigned ioapic_num)
 	unsigned apicid_base;
 	int siblings;
 	unsigned nb_cfg_54;
-        int bsp_apic_id = lapicid(); // bsp apicid
+	int bsp_apic_id = lapicid(); // bsp apicid
 
-        get_option(&disable_siblings, "multi_core");
+	get_option(&disable_siblings, "multi_core");
 
-        //get the nodes number
-        dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
-        nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1;
+	//get the nodes number
+	dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
+	nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1;
 
 	siblings = get_max_siblings(nodes);
 
@@ -111,9 +111,9 @@ unsigned get_apicid_base(unsigned ioapic_num)
 		and the kernel will try to get one that is small than 16 to make IOAPIC work.
 		I don't know when the kernel can support 256 APIC id. (APIC_EXT_ID is enabled) */
 
-	        //4:10 for two way  8:12 for four way 16:16 for eight way
+		//4:10 for two way  8:12 for four way 16:16 for eight way
 		//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
-	        apicid_base = nb_cfg_54 ? (siblings+1) * nodes :  8 * siblings + nodes;
+		apicid_base = nb_cfg_54 ? (siblings+1) * nodes :  8 * siblings + nodes;
 
 	}
 	else {
diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c
index 56f7dcc65e..79e9162c77 100644
--- a/src/cpu/amd/dualcore/dualcore.c
+++ b/src/cpu/amd/dualcore/dualcore.c
@@ -18,16 +18,16 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid)
 static inline uint8_t set_apicid_cpuid_lo(void)
 {
 #if !CONFIG_K8_REV_F_SUPPORT
-        if (is_cpu_pre_e0()) return 0; // pre_e0 can not be set
+	if (is_cpu_pre_e0()) return 0; // pre_e0 can not be set
 #endif
 
-        // set the NB_CFG[54]=1; why the OS will be happy with that ???
-        msr_t msr;
-        msr = rdmsr(NB_CFG_MSR);
-        msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
-        wrmsr(NB_CFG_MSR, msr);
+	// set the NB_CFG[54]=1; why the OS will be happy with that ???
+	msr_t msr;
+	msr = rdmsr(NB_CFG_MSR);
+	msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
+	wrmsr(NB_CFG_MSR, msr);
 
-        return 1;
+	return 1;
 }
 
 static inline void real_start_other_core(unsigned nodeid)
@@ -53,9 +53,9 @@ static inline void start_other_cores(void)
 		return; // disable multi_core
 	}
 
-        nodes = get_nodes();
+	nodes = get_nodes();
 
-        for (nodeid=0; nodeid<nodes; nodeid++) {
+	for (nodeid=0; nodeid<nodes; nodeid++) {
 		if ( get_core_num_in_bsp(nodeid) > 0) {
 			real_start_other_core(nodeid);
 		}
diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c
index bbfdd511e9..665f256f78 100644
--- a/src/cpu/amd/dualcore/dualcore_id.c
+++ b/src/cpu/amd/dualcore/dualcore_id.c
@@ -9,9 +9,9 @@
 //called by bus_cpu_scan too
 unsigned int read_nb_cfg_54(void)
 {
-        msr_t msr;
-        msr = rdmsr(NB_CFG_MSR);
-        return ( ( msr.hi >> (54-32)) & 1);
+	msr_t msr;
+	msr = rdmsr(NB_CFG_MSR);
+	return ( ( msr.hi >> (54-32)) & 1);
 }
 
 u32 get_initial_apicid(void)
@@ -27,17 +27,17 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54)
 	struct node_core_id id;
 	//    get the apicid via cpuid(1) ebx[27:24]
 	if ( nb_cfg_54) {
-                //   when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24]
-                id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
-                id.nodeid = (id.coreid>>CORE_ID_BIT);
-                id.coreid &= ((1<<CORE_ID_BIT)-1);
-        }
+		//   when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24]
+		id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
+		id.nodeid = (id.coreid>>CORE_ID_BIT);
+		id.coreid &= ((1<<CORE_ID_BIT)-1);
+	}
 	else
 	{
-                // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
-                id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;
-                id.coreid = (id.nodeid>>NODE_ID_BIT);
-                id.nodeid &= ((1<<NODE_ID_BIT)-1);
+		// when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
+		id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;
+		id.coreid = (id.nodeid>>NODE_ID_BIT);
+		id.nodeid &= ((1<<NODE_ID_BIT)-1);
 	}
 	return id;
 }