diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-30 21:22:40 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-30 21:22:40 +0000 |
| commit | 1d36d6df7dafea5a6f9dec80f4a3998470d440a2 (patch) | |
| tree | dd63064198bf6914420ab2b6c533d7578409d84c /src/cpu/amd/car | |
| parent | 8463dd9db0dc2ce02423775d0eb62e28aa01e9f9 (diff) | |
Use existing, readable MTRR #defines instead of hardcoding numbers.
Replace $0x200 with $MTRRphysBase_MSR(0) etc. Also, move some #ifdef stuff
a little bit around (should not affect any functionality) to make the
Intel/AMD/VIA CAR implementations more similar and easier to compare.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/car')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index e4f1ba426d..a365ca8e3c 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -243,13 +243,13 @@ clear_fixed_var_mtrr_out: #if CacheSize > 0x8000 /* enable caching for 32K-64K using fixed mtrr */ - movl $0x268, %ecx /* fix4k_c0000*/ + movl $MTRRfix4K_C0000_MSR, %ecx simplemask CacheSize, 0x8000 wrmsr #endif /* enable caching for 0-32K using fixed mtrr */ - movl $0x269, %ecx /* fix4k_c8000*/ + movl $MTRRfix4K_C8000_MSR, %ecx simplemask CacheSize, 0 wrmsr @@ -260,22 +260,23 @@ clear_fixed_var_mtrr_out: wrmsr #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) - /* enable write base caching so we can do execute in place - * on the flash rom. - */ - movl $0x202, %ecx - xorl %edx, %edx #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + + /* enable write base caching so we can do execute in place + * on the flash rom. + */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr - movl $0x203, %ecx + movl $MTRRphysMask_MSR(1), %ecx movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */ jmp_if_k8(wbcache_post_fam10_setup) movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */ |