diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2013-11-26 17:49:29 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-12-02 20:10:38 +0100 |
| commit | a6c29fe6841ad5e03ddb35803943bed3bc83dfd2 (patch) | |
| tree | 8d1250b77c57e4e0020cb2b027e8c395e0fa462b /src/cpu/amd/car/cache_as_ram.inc | |
| parent | 77a5abe78052ac8f65c005272700d82c2b014da7 (diff) | |
amd/car/post_cache_as_ram: Switch stack in assembly rather than in C
Compiler may do loads of optimisations around stack switch and so it's allowed
to break stack switch as it sees fit. Do it in assembly instead.
Not tested.
Change-Id: I277a62a9052e8fe9b04e7c65d149e087282ac2a2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4286
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/car/cache_as_ram.inc')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 7070cf9b10..8f0abce1a5 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -414,10 +414,22 @@ CAR_FAM10_ap_out: pushl %ebx /* Init detected. */ pushl %eax /* BIST */ call cache_as_ram_main + /* We will not go back. */ post_code(0xaf) /* Should never see this POST code. */ + .globl cache_as_ram_switch_stack + +cache_as_ram_switch_stack: + /* Return address. */ + popl %eax + /* Resume memory. */ + popl %eax + subl $(( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )), %esp + pushl %eax + call cache_as_ram_new_stack + all_mtrr_msrs: /* fixed MTRR MSRs */ .long MTRRfix64K_00000_MSR |