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| author | Yinghai Lu <yinghailu@gmail.com> | 2006-04-03 20:38:34 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2006-04-03 20:38:34 +0000 |
| commit | 9a791dffeae2097aa0a18f645ce07acfed41b9bc (patch) | |
| tree | 2d0359536fe3c1a0c313440b6be4ed09397dade9 /src/cpu/amd/car/cache_as_ram.inc | |
| parent | ffb7d8a31ae899f611235cd0a7f3579d34cd8cde (diff) | |
new cache_as_ram support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/car/cache_as_ram.inc')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index c7de4148a4..1cf141230b 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -1,8 +1,10 @@ /* by yhlu 6.2005 */ /* yhlu 2005.12 make it support HDT Memory Debuggers with Disassmbly, please select the PCI Bus mem for Phys Type*/ -/* We may need 4K bytes only */ +/* yhlu 2006.3 copy data from cache to ram and reserve 0x1000 for global variables */ #define CacheSize DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) +/* leave some space for global variable to pass to RAM stage */ +#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> @@ -147,7 +149,7 @@ clear_fixed_var_mtrr_out: #endif /*USE_FALLBACK_IMAGE == 1*/ /* set up the stack pointer */ - movl $(CacheBase+CacheSize-4), %eax + movl $(CacheBase+CacheSize - 4 - GlobalVarSize), %eax movl %eax, %esp /* Restore the BIST result */ |