diff options
| author | Stefan Reinauer <stepan@openbios.org> | 2005-12-01 10:54:44 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2005-12-01 10:54:44 +0000 |
| commit | 806e146e754a44f96c693cde707065b14f80d8a2 (patch) | |
| tree | e8e174faffc6f7674b93b5b34d17ef3fa716c32f /src/cpu/amd/car/cache_as_ram.inc | |
| parent | 70597f96c45e225a42f395cdf16b4ad62459dc3b (diff) | |
Applying 11_26_car_tyan.diff from Yinghai Lu.
NOTE: This will break the tree so it can be fixed up later
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/amd/car/cache_as_ram.inc')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index b8ec1ca407..79cee33206 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -9,19 +9,20 @@ /* Save the BIST result */ movl %eax, %ebp - // for normal part %ebx already contain cpu_init_detected from fallback call + /*for normal part %ebx already contain cpu_init_detected from fallback call */ -CacheAsRam: +cache_as_ram_setup: /* hope we can skip the double set for normal part */ #if USE_FALLBACK_IMAGE == 1 + /* check if cpu_init_detected */ movl $MTRRdefType_MSR, %ecx rdmsr andl $0x00000800, %eax - movl %eax, %ebx ; // We store the status about if cpu_init_detected + movl %eax, %ebx /* We store the status */ /* Set MtrrFixDramModEn for clear fixed mtrr */ - xorl %eax, %eax # clear %eax and %edx + xorl %eax, %eax xorl %edx, %edx enable_fixed_mtrr_dram_modify: @@ -97,13 +98,16 @@ clear_fixed_var_mtrr_out: xorl %edx, %edx movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr -#else +#endif /* USE_FALLBACK_IMAGE == 1*/ + +#if USE_FALLBACK_IMAGE == 0 + /* disable cache */ movl %cr0, %eax orl $(0x1<<30),%eax movl %eax, %cr0 -#endif /* USE_FALLBACK_IMAGE == 1*/ +#endif #if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) /* enable write base caching so we can do execute in place @@ -151,7 +155,7 @@ clear_fixed_var_mtrr_out: movl %esp, %ebp pushl %ebx /* init detected */ pushl %eax /* bist */ - call amd64_main + call cache_as_ram_main /* We will not go back */ fixed_mtrr_msr: @@ -169,4 +173,4 @@ var_iorr_msr: mem_top: .long 0xC001001A, 0xC001001D .long 0x000 /* NULL, end of table */ -.CacheAsRam_out: +cache_as_ram_setup_out: |