diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-06-01 13:27:00 -0700 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2020-06-03 03:59:08 +0000 |
| commit | 9ff79c22808fb88a5d5cb184a439d26ce00ac15b (patch) | |
| tree | 10c600b2454c547d610758aefc5ef48457066955 /src/cpu/amd/agesa | |
| parent | b763a4febcf7af67487cf2cf0038eebc61604a5a (diff) | |
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3197
Update FSP headers for Tiger Lake platform generated based FSP
version 3197, which includes below additional UPDs:
FSPM:
CmdMirror
RMTBIT
FSPS:
SataPortsEnableDitoConfig
BUG=b:157725468
BRANCH=none
TEST=build and boot volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I23d6baacc3d963b473280c7fdb1e5df950cd7ca8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41974
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/amd/agesa')
0 files changed, 0 insertions, 0 deletions