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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-08-07 14:44:51 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-08-09 00:38:39 +0200 |
| commit | 0db6820b10c3452764ab62173c3b75cefbf6c215 (patch) | |
| tree | 95abc6378ed60c37e14de842a7baf014dc60111b /src/cpu/amd/agesa | |
| parent | 4c29d7f27d315ab93c811fb86ba246151dc84da3 (diff) | |
Synchronize rdtsc instructions
The CPU can arbitrarily reorder calls to rdtsc, significantly
reducing the precision of timing using the CPUs time stamp counter.
Unfortunately the method of synchronizing rdtsc is different
on AMD and Intel CPUs. There is a generic method, using the cpuid
instruction, but that uses up a lot of registers, and is very slow.
Hence, use the correct lfence/mfence instructions (for CPUs that
we know support it)
Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1422
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/amd/agesa')
| -rw-r--r-- | src/cpu/amd/agesa/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 5ec5ce8b1d..b7e69e015a 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -25,6 +25,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15 default y if CPU_AMD_AGESA_FAMILY15_TN default n + select TSC_SYNC_LFENCE if CPU_AMD_AGESA |