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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-20 07:45:17 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-01 05:46:54 +0100 |
| commit | 036a581b8fa9478d4dba1bf9e576ee9cc0bead24 (patch) | |
| tree | 9b57756ad8ae88cb6287c43f9fcd351b55bace0e /src/cpu/amd/agesa | |
| parent | f08c8a5c2d34383ddadcf66a7e5c044907280fec (diff) | |
AGESA f14: Consolidate XIP cache
Do this like fam15tn to reduce code duplication.
Change-Id: I064fd27b85be7fb0c9d6918a84fc6f9b17065534
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17563
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd/agesa')
| -rw-r--r-- | src/cpu/amd/agesa/family14/fixme.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index d1bd0a1d78..ab10e3a704 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -92,6 +92,12 @@ void amd_initmmio(void) PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); } void amd_initenv(void) |