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authorAaron Durbin <adurbin@chromium.org>2013-04-01 15:40:45 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-04-03 19:25:17 +0200
commit0f0fe100cb27770d615a70d5a78310ad47cb1abf (patch)
treeb2284657a6c85335b7197f56d98fc5796ecd827b /src/cpu/amd/agesa
parentd46161e9eaaca8ec1d95f52461feb9647a99d5f3 (diff)
haswell: use new interface to disable rom caching
The haswell code was using the old assumption of which MTRR was used for the ROM cache. Now that there is an API for doing this use it as the old assumption is no longer valid. Change-Id: I59ef897becfc9834d36d28840da6dc4f1145b0c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3007 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/amd/agesa')
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