cpu/amd: Use common AMD's MSR

Phase 1. Due to the size of the effort, this CL is broken into several
phases.

Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

9 files changed, 33 insertions, 37 deletions

diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c
index d946e1bb13..084cae8456 100644
--- a/src/cpu/amd/agesa/family12/fixme.c
+++ b/src/cpu/amd/agesa/family12/fixme.c
@@ -14,6 +14,7 @@
  */
 
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/msr.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <AGESA.h>
 #include "amdlib.h"
@@ -75,7 +76,7 @@ void amd_initmmio(void)
 	   Address MSR register.
 	 */
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
+	LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
 
 	/* Enable Non-Post Memory in CPU */
 	PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index c2f3495eca..c81b18ea72 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -15,6 +15,8 @@
 
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <string.h>
@@ -23,13 +25,7 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/amd/multicore.h>
-#include <cpu/amd/amdfam12.h>
-
-#define MCG_CAP 0x179
-# define MCA_BANKS_MASK 0xff
-#define MC0_STATUS 0x401
 
 static void model_12_init(struct device *dev)
 {
@@ -55,12 +51,12 @@ static void model_12_init(struct device *dev)
 	disable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(MCG_CAP);
+	msr = rdmsr(IA32_MCG_CAP);
 	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
 	for (i = 0; i < num_banks; i++)
-		wrmsr(MC0_STATUS + (i * 4), msr);
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 
 	enable_cache();
 
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index 7d595853e6..33e164354e 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -14,7 +14,7 @@
  */
 
 #include <cpu/x86/mtrr.h>
-
+#include <cpu/amd/msr.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <AGESA.h>
 #include "amdlib.h"
@@ -78,7 +78,7 @@ void amd_initmmio(void)
 	   Address MSR register.
 	 */
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
+	LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
 
 	/* Set Ontario Link Data */
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0);
@@ -96,7 +96,7 @@ void amd_initmmio(void)
 
 	/* Set P-state 0 (1600 MHz) early to save a few ms of boot time */
 	MsrReg = 0;
-	LibAmdMsrWrite (0xC0010062, &MsrReg, &StdHeader);
+	LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader);
 }
 
 void amd_initenv(void)
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index b49d975761..3f0501e5cb 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -15,6 +15,8 @@
 
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <string.h>
@@ -23,15 +25,9 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam14.h>
 #include <arch/acpi.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
-#define MCG_CAP 0x179
-# define MCA_BANKS_MASK 0xff
-#define MC0_STATUS 0x401
-
 static void model_14_init(struct device *dev)
 {
 	u8 i;
@@ -78,12 +74,12 @@ static void model_14_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(MCG_CAP);
+	msr = rdmsr(IA32_MCG_CAP);
 	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
 	for (i = 0; i < num_banks; i++)
-		wrmsr(MC0_STATUS + (i * 4), msr);
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
 	setup_lapic();
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
index 2eb96891a0..847f75393f 100644
--- a/src/cpu/amd/agesa/family15tn/fixme.c
+++ b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -14,6 +14,7 @@
  */
 
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/msr.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <AGESA.h>
 #include "amdlib.h"
@@ -71,7 +72,7 @@ void amd_initmmio(void)
 	  Address MSR register.
 	*/
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+	LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index fdcb9a2332..d188bcc84b 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -15,8 +15,10 @@
 
 #include <console/console.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/smm.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <string.h>
 #include <cpu/x86/pae.h>
@@ -24,8 +26,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
@@ -73,12 +73,12 @@ static void model_15_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(MCG_CAP);
+	msr = rdmsr(IA32_MCG_CAP);
 	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
 	for (i = 0; i < num_banks; i++)
-		wrmsr(MC0_STATUS + (i * 4), msr);
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
 	setup_lapic();
@@ -108,14 +108,14 @@ static void model_15_init(struct device *dev)
 		printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
 
 		/* Set SMM base address for this CPU */
-		msr = rdmsr(MSR_SMM_BASE);
+		msr = rdmsr(SMM_BASE_MSR);
 		msr.lo = SMM_BASE - (cpu_idx * 0x400);
-		wrmsr(MSR_SMM_BASE, msr);
+		wrmsr(SMM_BASE_MSR, msr);
 
 		/* Enable the SMM memory window */
-		msr = rdmsr(MSR_SMM_MASK);
+		msr = rdmsr(SMM_MASK_MSR);
 		msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
-		wrmsr(MSR_SMM_MASK, msr);
+		wrmsr(SMM_MASK_MSR, msr);
 	}
 
 	/* Write protect SMM space with SMMLOCK. */
diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c
index 3d40fc3b33..7ff4c5c7a8 100644
--- a/src/cpu/amd/agesa/family15tn/udelay.c
+++ b/src/cpu/amd/agesa/family15tn/udelay.c
@@ -21,6 +21,7 @@
  */
 
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
 #include <cpu/x86/tsc.h>
 #include <delay.h>
 #include <stdint.h>
@@ -36,11 +37,11 @@ void udelay(uint32_t us)
 	tsc_start = rdtscll();
 
 	/* Get the P-state. This determines which MSR to read */
-	msr = rdmsr(0xc0010063);
+	msr = rdmsr(PS_STS_REG);
 	pstate_idx = msr.lo & 0x07;
 
 	/* Get FID and VID for current P-State */
-	msr = rdmsr(0xc0010064 + pstate_idx);
+	msr = rdmsr(PSTATE_0_MSR + pstate_idx);
 
 	/* Extract the FID and VID values */
 	fid = msr.lo & 0x3f;
diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c
index 4ea52cc6e0..1f22307f1e 100644
--- a/src/cpu/amd/agesa/family16kb/fixme.c
+++ b/src/cpu/amd/agesa/family16kb/fixme.c
@@ -14,6 +14,7 @@
  */
 
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/msr.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <AGESA.h>
 #include "amdlib.h"
@@ -71,7 +72,7 @@ void amd_initmmio(void)
 	  Address MSR register.
 	*/
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+	LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index 1b5db23ff5..286bcc377b 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -15,6 +15,8 @@
 
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/device.h>
 #include <string.h>
@@ -23,8 +25,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/amdfam16.h>
 #include <arch/acpi.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
@@ -71,12 +71,12 @@ static void model_16_init(struct device *dev)
 	x86_enable_cache();
 
 	/* zero the machine check error status registers */
-	msr = rdmsr(MCG_CAP);
+	msr = rdmsr(IA32_MCG_CAP);
 	num_banks = msr.lo & MCA_BANKS_MASK;
 	msr.lo = 0;
 	msr.hi = 0;
 	for (i = 0; i < num_banks; i++)
-		wrmsr(MC0_STATUS + (i * 4), msr);
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 
 	/* Enable the local CPU APICs */
 	setup_lapic();