diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-19 20:38:41 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-22 11:03:42 +0200 |
| commit | 65cc526f6f47755b4492cd9fc2134fb2dd067e90 (patch) | |
| tree | 9b7357287b96f73a762592ccc8b7d2153eff1d46 /src/cpu/amd/agesa/s3_resume.c | |
| parent | c5400efc11e181caf0babaa6001de18e3f23c6af (diff) | |
Ignore RAMTOP for MTRRs
Without RELOCATABLE_RAMSTAGE have WB cache large enough
to cover the greatest ramstage needs, as there is no benefit
of trying to accurately match the actual need. Choose
this to be bottom 16MiB.
With RELOCATABLE_RAMSTAGE write-back cache of low ram is
only useful for bottom 1MiB of RAM as a small part of this gets used
during SMP initialisation before proper MTRR setup.
Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/amd/agesa/s3_resume.c')
| -rw-r--r-- | src/cpu/amd/agesa/s3_resume.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 5f486f2fea..3a60b8d06c 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -75,11 +75,11 @@ static void set_resume_cache(void) msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); wrmsr(SYSCFG_MSR, msr); - /* Enable caching for 0 - coreboot ram using variable mtrr */ + /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ msr.lo = 0 | MTRR_TYPE_WRBACK; msr.hi = 0; wrmsr(MTRR_PHYS_BASE(0), msr); - msr.lo = ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; + msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; wrmsr(MTRR_PHYS_MASK(0), msr); |