diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-21 03:31:02 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-27 11:27:51 +0100 |
| commit | eaab6305beb587777248bf46a894050ed2a76b78 (patch) | |
| tree | 79de3d2d1e8eb82b432fcce7672b3f6cdea06a52 /src/cpu/amd/agesa/heapmanager.c | |
| parent | 12bb8f97b6e453ea2cc99607efb443025271f3d8 (diff) | |
cpu/amd/agesa/family15rl: Provide Richland CPU support
Richland -
Microarchitecture: Piledriver
Core stepping: RL-A1
CPUID: 610F31
Change-Id: I790085fbf36d836c903dcce77d794abb8578712b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7537
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/amd/agesa/heapmanager.c')
| -rw-r--r-- | src/cpu/amd/agesa/heapmanager.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index d2c39312d5..50ec3ffc51 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -28,7 +28,7 @@ void EmptyHeap(void) memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE); } -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) #define AGESA_RUNTIME_SIZE 4096 @@ -74,7 +74,7 @@ AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams->BufferPointer = NULL; -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) /* if the allocation is for runtime use simple CBMEM data */ if (Data == HEAP_CALLOUT_RUNTIME) return alloc_cbmem(AllocParams); |