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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-07 11:30:48 +0300
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 23:14:28 +0200
commit8b95c134207de9573f8e5eb758e5cee51741604a (patch)
tree8d49f7f9ce75bf9f0ae9ba26883588753e764f00 /src/cpu/amd/agesa/family15tn
parent3ad5a9b97f2d66764880e0cf01b1833d39ddd5ce (diff)
AMD: Kconfig cleanup
Change-Id: Ie347b32575c26133d52c275622d29d1cd4c6c0c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3623 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/cpu/amd/agesa/family15tn')
-rw-r--r--src/cpu/amd/agesa/family15tn/Kconfig19
1 files changed, 4 insertions, 15 deletions
diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig
index d2f5a8c1b2..9885570d88 100644
--- a/src/cpu/amd/agesa/family15tn/Kconfig
+++ b/src/cpu/amd/agesa/family15tn/Kconfig
@@ -22,59 +22,48 @@ config CPU_AMD_AGESA_FAMILY15_TN
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
+if CPU_AMD_AGESA_FAMILY15_TN
+
config CPU_ADDR_BITS
int
default 48
- depends on CPU_AMD_AGESA_FAMILY15_TN
config CPU_SOCKET_TYPE
hex
default 0x10
- depends on CPU_AMD_AGESA_FAMILY15_TN
# DDR2 and REG
config DIMM_SUPPORT
hex
default 0x0104
- depends on CPU_AMD_AGESA_FAMILY15_TN
config EXT_RT_TBL_SUPPORT
bool
default n
- depends on CPU_AMD_AGESA_FAMILY15_TN
config EXT_CONF_SUPPORT
bool
default n
- depends on CPU_AMD_AGESA_FAMILY15_TN
config CBB
hex
default 0x0
- depends on CPU_AMD_AGESA_FAMILY15_TN
config CDB
hex
default 0x18
- depends on CPU_AMD_AGESA_FAMILY15_TN
-
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_AGESA_FAMILY15_TN
config XIP_ROM_SIZE
hex
default 0x100000
- depends on CPU_AMD_AGESA_FAMILY15_TN
config HAVE_INIT_TIMER
bool
default y
- depends on CPU_AMD_AGESA_FAMILY15_TN
config HIGH_SCRATCH_MEMORY_SIZE
hex
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
default 0xA1000
- depends on CPU_AMD_AGESA_FAMILY15_TN
+
+endif