diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-15 21:37:48 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-20 18:14:34 +0000 |
| commit | 520717dff196e1d1ed61f72a8abadbc114ee6ba1 (patch) | |
| tree | 5658d5fb27c6f5901c9b714fd1c6839ed36e28f9 /src/cpu/amd/agesa/family15tn | |
| parent | b9bd69e70ed355d89ff41d66ed7134338c5986fe (diff) | |
AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/amd/agesa/family15tn')
| -rw-r--r-- | src/cpu/amd/agesa/family15tn/fixme.c | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index e92aa9a9bf..03c6503300 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -60,22 +60,3 @@ void amd_initcpuio(void) PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } - -void amd_initmmio(void) -{ - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); -} |